Merge. Write RO ELF sections to memory via Zisk instructions.

0xPolygonHermez · Nov 9, 2024 · 2494dbb · 2494dbb
2 parents 264a2fd + 2672ca8
commit 2494dbb
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Showing 26 changed files with 294 additions and 161 deletions.
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -26,12 +26,12 @@ opt-level = 3
 opt-level = 3
 
 [workspace.dependencies]
-proofman-common = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", branch ="develop" }
-proofman-macros = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", branch ="develop" }
-proofman-util = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", branch ="develop" }
-proofman = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", branch ="develop" }
-pil-std-lib = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", branch ="develop" }
-stark = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", branch ="develop" }
+proofman-common = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", rev = "0.0.10" }
+proofman-macros = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", rev = "0.0.10" }
+proofman-util = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", rev = "0.0.10" }
+proofman = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", rev = "0.0.10" }
+pil-std-lib = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", rev = "0.0.10" }
+stark = { git = "https://github.com/0xPolygonHermez/pil2-proofman.git", rev = "0.0.10" }
 #Local development
 # proofman-common = { path = "../pil2-proofman/common" }
 # proofman-macros = { path = "../pil2-proofman/macros" }

diff --git a/core/src/mem.rs b/core/src/mem.rs
@@ -32,18 +32,19 @@ impl Mem {
         }
         self.read_sections.push(mem_section);
         /*println!(
-            "Mem::add_read_section() start={:x}={} len={} end={:x}={}",
+            "Mem::add_read_section() start={:x}={} len={:x}={} end={:x}={}",
             start,
             start,
             buffer.len(),
+            buffer.len(),
             end,
             end
         );*/
     }
 
     /// Adds a write section to the memory structure, which cannot be written twice
     pub fn add_write_section(&mut self, start: u64, size: u64) {
-        //println!("Mem::add_write_section() start={} size={}", start, size);
+        //println!("Mem::add_write_section() start={:?}={} size={}", start, start, size);
 
         // Check the start address is not zero
         if start == 0 {
@@ -146,8 +147,24 @@ impl Mem {
         //println!("Mem::write() addr={:x}={} width={} value={:x}={}", addr, addr, width, val,
         // val);
 
-        // Get a reference to the write section
-        let section = &mut self.write_section;
+        // Search for the section that contains the address using binary search (dicothomic search)
+        let section = if let Ok(section) = self.read_sections.binary_search_by(|section| {
+            if addr < section.start {
+                std::cmp::Ordering::Greater
+            } else if addr > (section.end - width) {
+                std::cmp::Ordering::Less
+            } else {
+                std::cmp::Ordering::Equal
+            }
+        }) {
+            &mut self.read_sections[section]
+        } else {
+            /*panic!(
+                "Mem::write_silent() section not found for addr={:x}={} with width: {}",
+                addr, addr, width
+            );*/
+            &mut self.write_section
+        };
 
         // Check that the address and width fall into this section address range
         if (addr < section.start) || ((addr + width) > section.end) {

diff --git a/core/src/zisk_required_operation.rs b/core/src/zisk_required_operation.rs
@@ -8,7 +8,7 @@ pub struct ZiskRequiredOperation {
     pub b: u64,
 }
 
-#[derive(Clone)]
+#[derive(Clone, Debug)]
 pub struct ZiskRequiredMemory {
     pub step: u64,
     pub is_write: bool,

diff --git a/emulator/src/emu_context.rs b/emulator/src/emu_context.rs
@@ -69,6 +69,29 @@ impl EmuContext {
 
 impl Default for EmuContext {
     fn default() -> Self {
-        Self::new(Vec::new())
+        let ctx = EmuContext {
+            inst_ctx: InstContext {
+                mem: Mem::new(),
+                a: 0,
+                b: 0,
+                c: 0,
+                flag: false,
+                sp: 0,
+                pc: ROM_ENTRY,
+                step: 0,
+                end: false,
+            },
+            tracerv: Vec::new(),
+            tracerv_step: 0,
+            tracerv_current_regs: [0; 32],
+            trace_pc: 0,
+            trace: EmuTrace::default(),
+            do_callback: false,
+            callback_steps: 0,
+            last_callback_step: 0,
+            do_stats: false,
+            stats: Stats::default(),
+        };
+        ctx
     }
 }
diff --git a/rom-merkle/src/main.rs b/rom-merkle/src/main.rs
@@ -84,7 +84,7 @@ fn main() {
     let buffer_allocator: Arc<StarkBufferAllocator> =
         Arc::new(StarkBufferAllocator::new(proving_key_path.to_path_buf()));
     let global_info = GlobalInfo::new(global_info_path);
-    let sctx: Arc<SetupCtx> = Arc::new(SetupCtx::new(&global_info, &ProofType::Basic));
+    let sctx = Arc::new(SetupCtx::new(&global_info, &ProofType::Basic));
 
     if let Err(e) =
         RomSM::<Goldilocks>::compute_trace(rom_path.to_path_buf(), buffer_allocator, &sctx)

diff --git a/state-machines/arith/src/arith.rs b/state-machines/arith/src/arith.rs
@@ -74,8 +74,8 @@ impl<F> WitnessComponent<F> for ArithSM {
         _stage: u32,
         _air_instance: Option<usize>,
         _pctx: Arc<ProofCtx<F>>,
-        _ectx: Arc<ExecutionCtx>,
-        _sctx: Arc<SetupCtx>,
+        _ectx: Arc<ExecutionCtx<F>>,
+        _sctx: Arc<SetupCtx<F>>,
     ) {
     }
 }

diff --git a/state-machines/arith/src/arith_32.rs b/state-machines/arith/src/arith_32.rs
@@ -56,8 +56,8 @@ impl<F> WitnessComponent<F> for Arith32SM {
         _stage: u32,
         _air_instance: Option<usize>,
         _pctx: Arc<ProofCtx<F>>,
-        _ectx: Arc<ExecutionCtx>,
-        _sctx: Arc<SetupCtx>,
+        _ectx: Arc<ExecutionCtx<F>>,
+        _sctx: Arc<SetupCtx<F>>,
     ) {
     }
 }

diff --git a/state-machines/arith/src/arith_3264.rs b/state-machines/arith/src/arith_3264.rs
@@ -58,8 +58,8 @@ impl<F> WitnessComponent<F> for Arith3264SM {
         _stage: u32,
         _air_instance: Option<usize>,
         _pctx: Arc<ProofCtx<F>>,
-        _ectx: Arc<ExecutionCtx>,
-        _sctx: Arc<SetupCtx>,
+        _ectx: Arc<ExecutionCtx<F>>,
+        _sctx: Arc<SetupCtx<F>>,
     ) {
     }
 }

diff --git a/state-machines/arith/src/arith_64.rs b/state-machines/arith/src/arith_64.rs
@@ -53,8 +53,8 @@ impl<F> WitnessComponent<F> for Arith64SM {
         _stage: u32,
         _air_instance: Option<usize>,
         _pctx: Arc<ProofCtx<F>>,
-        _ectx: Arc<ExecutionCtx>,
-        _sctx: Arc<SetupCtx>,
+        _ectx: Arc<ExecutionCtx<F>>,
+        _sctx: Arc<SetupCtx<F>>,
     ) {
     }
 }

diff --git a/state-machines/arith/src/arith_traces.rs b/state-machines/arith/src/arith_traces.rs
@@ -1,6 +1,6 @@
 use proofman_common as common;
 pub use proofman_macros::trace;
 
-trace!(Arith320Row, Arith320Trace<F> { fake: F });
-trace!(Arith640Row, Arith640Trace<F> { fake: F });
-trace!(Arith32640Row, Arith32640Trace<F> { fake: F });
+trace!(Arith32Row, Arith32Trace<F> { fake: F });
+trace!(Arith64Row, Arith64Trace<F> { fake: F });
+trace!(Arith3264Row, Arith3264Trace<F> { fake: F });
diff --git a/state-machines/common/src/lib.rs b/state-machines/common/src/lib.rs
@@ -13,8 +13,8 @@ pub use temp::*;
 pub use worker::*;
 
 pub fn create_prover_buffer<F>(
-    ectx: &ExecutionCtx,
-    sctx: &SetupCtx,
+    ectx: &ExecutionCtx<F>,
+    sctx: &SetupCtx<F>,
     airgroup_id: usize,
     air_id: usize,
 ) -> (Vec<F>, u64) {

diff --git a/state-machines/freq-ops/src/freq_ops.rs b/state-machines/freq-ops/src/freq_ops.rs
@@ -48,8 +48,8 @@ impl<F> WitnessComponent<F> for FreqOpsSM {
         _stage: u32,
         _air_instance: Option<usize>,
         _pctx: Arc<ProofCtx<F>>,
-        _ectx: Arc<ExecutionCtx>,
-        _sctx: Arc<SetupCtx>,
+        _ectx: Arc<ExecutionCtx<F>>,
+        _sctx: Arc<SetupCtx<F>>,
     ) {
     }
 }

diff --git a/state-machines/freq-ops/src/freq_ops_trace.rs b/state-machines/freq-ops/src/freq_ops_trace.rs
@@ -1,4 +1,4 @@
 use proofman_common as common;
 pub use proofman_macros::trace;
 
-trace!(FreqOps0Row, FreqOps0Trace<F> { fake: F });
+trace!(FreqOpsRow, FreqOpsTrace<F> { fake: F });
diff --git a/state-machines/main/pil/main.pil b/state-machines/main/pil/main.pil
@@ -112,8 +112,6 @@ airtemplate Main(int N = 2**21, int RC = 2, int stack_enabled = 0, const int ope
     col witness jmp_offset1, jmp_offset2;  // if flag, goto2, else goto 1
     col witness m32;
 
-    const expr addr_step = STEP * 3;
-
     const expr sel_mem_b;
 
     sel_mem_b = b_src_mem + b_src_ind;
@@ -135,29 +133,31 @@ airtemplate Main(int N = 2**21, int RC = 2, int stack_enabled = 0, const int ope
     }
 
     // Mem.load
-    //mem_load(sel: a_src_mem,
-    //         step: addr_step,
-    //         addr: addr0,
-    //         value: a);
+    mem_load(sel: a_src_mem,
+             step: STEP,
+             addr: addr0,
+             value: a);
 
     // Mem.load
-    //mem_load(sel: sel_mem_b,
-    //          step: addr_step + 1,
-    //          bytes: ind_width,
-    //          addr: addr1,
-    //          value: b);
+    mem_load(sel: sel_mem_b,
+             step: STEP,
+             step_offset: 1,
+             bytes: ind_width,
+             addr: addr1,
+             value: b);
 
     const expr store_value[2];
 
     store_value[0] = store_ra*(pc + jmp_offset2 - c[0]) + c[0];
     store_value[1] = (1 - store_ra) * c[1];
 
     // Mem.store
-    //mem_store(sel: store_mem + store_ind,
-    //          step: addr_step + 2,
-    //          bytes: ind_width,
-    //          addr: addr2,
-    //          value: store_value);
+    mem_store(sel: store_mem + store_ind,
+              step: STEP,
+              step_offset: 2,
+              bytes: ind_width,
+              addr: addr2,
+              value: store_value);
 
     // Operation.assume => how organize software
     col witness __debug_operation_bus_enabled;