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README.md

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+# KW6502 - Koen van Wijngaarden's 6502 Computer
+
+This repository contains some of the work in progress during my build of Ben Eater's inspired 6502 8-bit computer similar 
+to typical machines of the early 1980s. If you haven't seen Ben's videos, I would strongly suggest you start there:
+[Ben Eater's 6502 project](https://eater.net/6502)
+
+
+## What is different
+
+Compared to Ben's 6502 build I introduced the following changes:
+1. Changed [address decoder logic](Schematics/README.md#address-decoder-change)
+2. Added [ACIA chip for serial communication](Schematics/README.md#extra-acia-chip-for-serial-communication)
+3. Changed [compiler from VASM to CC65](Schematics/README.md#migration-from-vasm-to-cc65)
+4. Changed [system clock to 1.8432 MHz](Schematics/README.md#changed-system-clock)

Schematics/README.md

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+# 6502 System Schematics
+
+This documentation provides all the information regarding my variant of BE6502 computer
+
+*The schematic schematic is work in progress*
+
+## Deviations from Ben Eater's design
+
+This section describes details of each deviation from original BE6502 design.
+
+### Address decoder change
+As Ben explained in his video, there are many ways to handle address decoding logic and he opted for model with 16K RAM,
+8K VIA shadow and 32K ROM. He does note that it's a bit of a waste, 
+but given the simplicity of the project it should not be a problem - and he is absolutely right.
+
+I wanted more with my build. I wanted to test my understanding of how address decoding works.
+My build provides 24K RAM, 4K VIA shadow, 4K ACIA shadow and 32K ROM.
+
+![Address Compare Image](../blob/main/Schematics/address-compare.png?raw=true)
+
+| Segment | BE6502        | KW6502        |
+|---------|---------------|---------------|
+| RAM     | 0x0000-0x3fff | 0x0000-0x5fff |
+| ACIA    |               | 0x6000        |
+| VIA     | 0x6000        | 0x7000        |
+| ROM     | 0x8000-0xffff | 0x8000-0xffff |