pipeline

pipeline verilog, The final project of computer architect

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
ALU.v		ALU.v
ALUController.v		ALUController.v
And gate.v		And gate.v
DataMem.v		DataMem.v
EXE2MEM.v		EXE2MEM.v
ID2EXE.v		ID2EXE.v
IF2ID.v		IF2ID.v
InstMem.v		InstMem.v
LShift.v		LShift.v
MEM2WB.v		MEM2WB.v
MIPS(Main).v		MIPS(Main).v
Mux 2-1.v		Mux 2-1.v
PC.v		PC.v
README.md		README.md
RegFile.v		RegFile.v
adder.v		adder.v
beq.v		beq.v
controller.v		controller.v
photo_2019-05-27_15-22-35.jpg		photo_2019-05-27_15-22-35.jpg
signext.v		signext.v
testBench.v		testBench.v
گزارش.pdf		گزارش.pdf

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