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svx6.stp
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svx6.stp
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' Stapl file for downloading two SVXs
' Version 2, 2015-03-10 by &RA chip[01:05):latency=6, chip(06:12):latency=40
' Version 3, 2015-03-17 by &RA Latency changed to 40 in all chips
' Version 4, 2015-03-18 by &RA RTPS on
' The FEM should be properly initialized before, i.e. ./stapl_cmdline.py i10 10000000 00100000 240
' And CARB too: i.e. ./stapl_cmdline.py -g i10 17e
' FYI, the python command to reverse the bit order:
' hex(int('{:0192b}'.format(0x020101010101010101010101010101014614c087c4003007)[::-1], 2))
' $e00c0023e103286280808080808080808080808080808040
' $ 3 2 120 9 8 7 6 5 4 3 2 110 9 8 7 6 5 4 3 2 1 0
' #.9.........8.........7.........6.........5.........4.........3.........2.........1.........0.........9.........8.........7.........6.........5.........4.........3.........2.........1.........;
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx.......2.........1.........0.........9.........8.........7.........6.........5.........4.........3.........2.........1.........;
' #111000000000100000001000001010111110010000000011001011000110001010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001
ACTION TRANS = DO_TRANS;
DATA PARAMETERS;
BOOLEAN chip1[192];
BOOLEAN chip2[192];
BOOLEAN irdata[10*32];
ENDDATA;
PROCEDURE DO_TRANS USES PARAMETERS;
' Load sequencer with single command '18'
IRSCAN 8, $16, CAPTURE irdata[7..0];
DRSCAN 32, $1ff00000, CAPTURE irdata[31..0];
DRSCAN 32, $00000018, CAPTURE irdata[31..0];
DRSCAN 32, $00120000, CAPTURE irdata[31..0];
DRSCAN 32, $80200000, CAPTURE irdata[31..0];
' Start downloading
IRSCAN 8, $18, CAPTURE irdata[7..0];
'Last chip flag = 0
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100100000000100000001111001010111110011100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip12:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111111101100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip11:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111110101100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip10:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111111001100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip09:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111110001100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip08:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111111110100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip07:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111110110100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip06:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111111010100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip05:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111110010100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip04:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111111100100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip03:", chip1[191..0];
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100000000000100000001111001010111110100100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip02:", chip1[191..0];
'First chip flag = 0
' #.9.LF......8.........RRG.......6...^^ID^^^.^Lat^^IRIWIsel^BW^DVx
DRSCAN 192, #100010000000100000001111001010111111000100010100001011000111101010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000001, CAPTURE chip1[191..0];
EXPORT "Shifted out chip01:", chip1[191..0];
ENDPROC;