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Implementation of an ARM processor with hazard and forwarding units, along with SRAM and cache memory

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ARM		ARM
CACHE		CACHE
ForwardingUnit		ForwardingUnit
ID		ID
IF		IF
SRAM		SRAM
LICENSE		LICENSE
README.md		README.md
final_report.pdf		final_report.pdf

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Computer-Architecture-Lab-Projects

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Implementation of an ARM processor with hazard and forwarding units, along with SRAM and cache memory

arm processor-design single-cycle-processor multi-cycle-processor pipeline-architecture

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