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This is a simple CPU using myHDL package.

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Name		Name	Last commit message	Last commit date
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Project_1		Project_1
Project_2_Blocks		Project_2_Blocks
Project_2_CPU_TOP_only		Project_2_CPU_TOP_only
EE_361_final_project_report.pdf		EE_361_final_project_report.pdf
README.md		README.md
datapath.png		datapath.png

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myHDL-project

This is a simple CPU using myHDL package in python. King abdulaziz university

CPU datapath

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This is a simple CPU using myHDL package.

python cpu verilog myhdl assebly myhdl-models

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