From 6a5f8b1bcdbdbc6831271662e9ab4c818781c508 Mon Sep 17 00:00:00 2001 From: Julie Schwartz Date: Sat, 6 Apr 2024 22:10:18 +1300 Subject: [PATCH] Testsuite: Add "which_mach" and use in div-by-zero tests The divmod tests fail on arm64, because the tests are expecting SIGFPE error to be raised, but ARM does not. This may need to be addressed in the code generation for Bluesim, but in the meantime, update the test to expect no error when the MACHTYPE is arm64. A new "which_mach" procedure in the testsuite allows querying MACHTYPE. Found an old test that was calling "uname -m" to get the machtype, and test for x86_64. This could be replaced with a call to "which_mach", but the use was to workaround a bug in iverilog 0.8.3, which is older than we need to support, so instead the code is just removed. --- testsuite/bsc.misc/divmod/divmod.exp | 8 ++++++-- .../bsc.names/portRenaming/misc/misc.exp | 19 +------------------ testsuite/config/unix.exp | 10 ++++++++++ testsuite/suitemake.mk | 7 ++++++- 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/testsuite/bsc.misc/divmod/divmod.exp b/testsuite/bsc.misc/divmod/divmod.exp index 0e0c6666c..cc82f103c 100644 --- a/testsuite/bsc.misc/divmod/divmod.exp +++ b/testsuite/bsc.misc/divmod/divmod.exp @@ -7,13 +7,17 @@ test_c_veri_bsv_modules_options DivMod {} "-no-use-negate" test_c_veri_bsv_modules_options DivModWide {} "-no-use-negate" sysDivModWide.out.expected -# expected status for darwin rh3 and rh4 set fpe [list SIGFPE 8 136] # Test that divide-by-zero produces some failure in Bluesim compile_object_pass DivideByZero.bsv sysDivideByZero link_objects_pass sysDivideByZero sysDivideByZero -sim_output_status sysDivideByZero $fpe +if [string equal [which_mach] "arm64"] { + # This is an expected bug (GitHub #688) + sim_output_status sysDivideByZero 0 +} else { + sim_output_status sysDivideByZero $fpe +} # In Verilog it silently produces x's test_veri_only_bsv DivideByZero sysDivideByZero.v.out.expected diff --git a/testsuite/bsc.names/portRenaming/misc/misc.exp b/testsuite/bsc.names/portRenaming/misc/misc.exp index c24d4cc7c..0cae78f61 100644 --- a/testsuite/bsc.names/portRenaming/misc/misc.exp +++ b/testsuite/bsc.names/portRenaming/misc/misc.exp @@ -6,26 +6,9 @@ if { $vtest == 1 } { -proc test_iverilog_version_and_machine_type {} { - global verilog_compiler - set code [catch "exec $verilog_compiler -V 2>/dev/null | head -1" x2] - set mach [exec uname -m] - set x86_64 [string first "x86_64" $mach] - set icarus [string first "Icarus Verilog" $x2] - set version [string first "0.8.3" $x2] - return [expr {$x86_64 == -1 || $icarus == -1 || $version == -1}] -} - compile_object_pass Small1.bsv compile_verilog_pass Small1.bsv -if [ test_iverilog_version_and_machine_type ] { - # this test is known to fail for x86_64 for iverilog 0.8.3 - # due to a bug (assertion failure) in iverilog - link_verilog_no_main_pass {Tb1.v mkSmallTest1.v} Tb1 -} else { - verbose -log "Skipping Tb1 verilog link test" -} - +link_verilog_no_main_pass {Tb1.v mkSmallTest1.v} Tb1 compile_object_pass Small2.bsv compile_verilog_pass Small2.bsv diff --git a/testsuite/config/unix.exp b/testsuite/config/unix.exp index 6a456ab71..93e41c8e2 100644 --- a/testsuite/config/unix.exp +++ b/testsuite/config/unix.exp @@ -200,6 +200,15 @@ proc which_os {} { return $env(OSTYPE) } +proc which_mach {} { + global env + if {! [info exists env(MACHTYPE)]} { + perror "can't find architecture -- set MACHTYPE to the name" + exit 1 + } + return $env(MACHTYPE) +} + # return true if the given Bluetcl packahe is available proc bluetcl_package_available { pkg } { global bluetcl @@ -3209,6 +3218,7 @@ verbose -log "Do internal checks is [do_internal_checks]" 1 # System settings verbose -log "Operating system is [which_os]" 1 +verbose -log "Architecture is [which_mach]" 1 # Assume 64-bit set ::is64 "64" diff --git a/testsuite/suitemake.mk b/testsuite/suitemake.mk index 5c81fe435..b70195a6b 100644 --- a/testsuite/suitemake.mk +++ b/testsuite/suitemake.mk @@ -7,6 +7,9 @@ ifneq ($(TEST_OSTYPE), $(findstring $(TEST_OSTYPE), Linux Darwin)) $(error TEST_OSTYPE environment not recognized: $(TEST_OSTYPE)) endif +TEST_MACHTYPE ?= $(shell $(CONFDIR)/../platform.sh machtype) +# TODO: Test for expected architectures? + MAKEFLAGS += --no-print-directory # Make sure that the environments are consistent @@ -64,7 +67,9 @@ RUNTESTENV = MAKEFLAGS= BSCTEST=1 \ BSC_VERILOG_SIM=$(TEST_BSC_VERILOG_SIM) \ TEST_CONFIG_DIR=${TEST_CONFIG} \ BLUETCL=$(TEST_BLUETCL) \ - OSTYPE=$(TEST_OSTYPE) LC_ALL=$(LC_ALL) \ + OSTYPE=$(TEST_OSTYPE) \ + MACHTYPE=$(TEST_MACHTYPE) \ + LC_ALL=$(LC_ALL) \ SYSTEMC_INC=$(TEST_SYSTEMC_INC) \ SYSTEMC_LIB=$(TEST_SYSTEMC_LIB) \ SYSTEMC_CXXFLAGS=$(TEST_SYSTEMC_CXXFLAGS) \