From bae6dba41744420b3053dd41032fb48eeca8d7a6 Mon Sep 17 00:00:00 2001 From: Austin Seipp Date: Tue, 24 Aug 2021 04:06:14 -0500 Subject: [PATCH] chore(comp): remove -v95 flag Remove all support code for Verilog 95 compatibility. Not only is V95 ancient, it also doesn't support necessary features like vendor-agnostic attributes, which we will want to use in the future. This also deletes the relevant tests and simplifies a little of the pretty- printing code, too. Signed-off-by: Austin Seipp --- doc/user_guide/user_guide.tex | 10 ------ src/comp/AVerilogUtil.hs | 28 ++++------------ src/comp/Flags.hs | 1 - src/comp/FlagsDecode.hs | 6 ---- src/comp/GenABin.hs | 10 +++--- src/comp/GenBin.hs | 2 +- src/comp/Verilog.hs | 13 +++----- testsuite/bsc.options/bsc.help.out.expected | 1 - .../bsc.print-flags-raw.out.expected | 1 - testsuite/bsc.verilog/v95/Makefile | 7 ---- testsuite/bsc.verilog/v95/Param.v | 29 ----------------- testsuite/bsc.verilog/v95/ParamOrder.bsv | 32 ------------------- testsuite/bsc.verilog/v95/Signed.bsv | 14 -------- .../v95/sysParamOrder.out.expected | 3 -- .../bsc.verilog/v95/sysSigned.out.expected | 14 -------- .../v95/sysSigned.v95.out.expected | 14 -------- testsuite/bsc.verilog/v95/v95.exp | 20 ------------ 17 files changed, 17 insertions(+), 188 deletions(-) delete mode 100644 testsuite/bsc.verilog/v95/Makefile delete mode 100644 testsuite/bsc.verilog/v95/Param.v delete mode 100644 testsuite/bsc.verilog/v95/ParamOrder.bsv delete mode 100644 testsuite/bsc.verilog/v95/Signed.bsv delete mode 100644 testsuite/bsc.verilog/v95/sysParamOrder.out.expected delete mode 100644 testsuite/bsc.verilog/v95/sysSigned.out.expected delete mode 100644 testsuite/bsc.verilog/v95/sysSigned.v95.out.expected delete mode 100644 testsuite/bsc.verilog/v95/v95.exp diff --git a/doc/user_guide/user_guide.tex b/doc/user_guide/user_guide.tex index 8856057c0..a0c03c21c 100644 --- a/doc/user_guide/user_guide.tex +++ b/doc/user_guide/user_guide.tex @@ -1687,7 +1687,6 @@ \subsection{Verilog back-end} back end. \index{-remove-unused-modules@\te{-remove-unused-modules} (compiler flag)} -\index{-v95@\te{-v95} (compiler flag)} \index{-remove-dollar@\te{-remove-dollar} (compiler flag)} \index{-unspecified-to@\te{-unspecified-to} (compiler flag)} \index{-Xv@\te{-Xv} (compiler flag)} @@ -1695,7 +1694,6 @@ \subsection{Verilog back-end} \index{-use-dpi@\te{-use-dpi}} \begin{centerboxverbatim} -remove-unused-modules remove unconnected modules from the Verilog --v95 generate strict Verilog 95 code -unspecified-to val remaining unspecified values are set to: 'X', '0', '1', 'Z', or 'A' -remove-dollar remove dollar signs from Verilog identifiers @@ -1711,14 +1709,6 @@ \subsection{Verilog back-end} should be used on modules undergoing synthesis, and not be used for testbench modules. -The {\bf\tt -v95} flag restricts the Verilog output to pure Verilog-95. -By default, the Verilog output uses features which are not in the -Verilog-95 standard. These features include passing module -parameters by name and use of the {\tt \$signed} system task for formatting -{\tt \$display} output. When the {\tt -v95} flag is turned on, uses -of these features are removed, but comments are left in the Verilog -indicating the parameter names or system tasks which were removed. - The {\bf\tt -unspecified-to val} flag defines the value which any remaining unspecified values should be tied to. The valid set of values are: {\tt X}, {\tt 0}, {\tt 1}, {\tt Z}, or {\tt A}, diff --git a/src/comp/AVerilogUtil.hs b/src/comp/AVerilogUtil.hs index 36b06f395..ac6753cd4 100644 --- a/src/comp/AVerilogUtil.hs +++ b/src/comp/AVerilogUtil.hs @@ -37,7 +37,7 @@ import Data.Maybe import FStringCompat(FString, getFString) import ErrorUtil -import Flags(Flags, readableMux, unSpecTo, v95, systemVerilogTasks, useDPI) +import Flags(Flags, readableMux, unSpecTo, systemVerilogTasks, useDPI) import PPrint import IntLit import Id @@ -71,8 +71,6 @@ import SCC(tsort) -- Define a structure which controls Verilog conversions data VConvtOpts = VConvtOpts { vco_unspec :: String, - vco_v95 :: Bool, - vco_v95_tasks :: [String], vco_readableMux :: Bool, vco_sv_tasks :: Bool, vco_use_dpi :: Bool @@ -82,8 +80,6 @@ data VConvtOpts = VConvtOpts { flagsToVco :: Flags -> VConvtOpts flagsToVco flags = VConvtOpts { vco_unspec = unSpecTo flags, - vco_v95 = v95 flags, - vco_v95_tasks = ["$signed", "$unsigned"], vco_readableMux = readableMux flags, vco_sv_tasks = systemVerilogTasks flags, vco_use_dpi = useDPI flags @@ -215,7 +211,7 @@ vForeignCall vco f@(AForeignCall aid taskid (c:es) ids resets) ffmap = if aid==idSVA then fcall es else foldr (Vif . mkNotEqualsReset . vExpr vco) fcall_body resets where - vtaskid = VId (vCommentTaskName vco taskid) aid Nothing + vtaskid = VId taskid aid Nothing (ids',es') = let lv = headOrErr "vForeignCall: missing return value" ids in case isAForeignCallWithRetAsArg vco ffmap f of (Just ty) -> ([], (ASDef ty lv) : es) @@ -541,7 +537,7 @@ vDefMpd vco (ADef i t vi_module_name = mkVId n, vi_inst_name = VId inst_name i Nothing, -- these are size params, so default width of 32 is fine - vi_inst_params = Left (map (\x -> (Nothing,VEConst x)) is), + vi_inst_params = Left (map (\x -> VEConst x) is), vi_inst_ports = (zip (map (mkVId . fst) ips') (map (Just . (vExpr vco)) es') @@ -582,7 +578,7 @@ vDefMpd vco (ADef i_t t_t@(ATBit _) fn@(AFunCall {}) _) ffmap [ VMDecl $ VVDecl VDReg (vSize t_t) [VVar (vId i_t)] , VMStmt { vi_translate_off = True, vi_body = body } ] - where name = vCommentTaskName vco (vNameToTask (vco_use_dpi vco) (ae_funname fn)) + where name = vNameToTask (vco_use_dpi vco) (ae_funname fn) vtaskid = VId name (ae_objid fn) Nothing sensitivityList = nub (concatMap aIds (ae_args fn)) ev = foldr1 VEEOr (map (VEE . VEVar) sensitivityList) @@ -685,7 +681,7 @@ vExpr vco (APrim aid t p es) = VEOp (idToVId aid) (vExpr vco (APrim aid t p (ini -- vExpr vco (AMethCall t i m _) = internalError "AVerilog.vExpr: AMethCall with args" -- vExpr vco (AMethValue t i m) = VEVar (vMethId i m 1 MethodResult M.Empty) vExpr vco (AFunCall _ _ n isC es) = - let name = vCommentTaskName vco (if isC then vNameToTask (vco_use_dpi vco) n else n) + let name = if isC then vNameToTask (vco_use_dpi vco) n else n in VEFctCall (mkVId name) (map (vExpr vco) es) vExpr vco (ASInt idt (ATBit w) (IntLit _ b i)) = VEWConst (idToVId idt) w b i vExpr vco (ASReal _ _ r) = VEReal r @@ -768,9 +764,7 @@ muxInst vco pri s i es = ++ "Mux_" ++ itos (length es `div` 2)), vi_inst_name = i, - vi_inst_params = if ( vco_v95 vco ) - then Left [(Just $ getVIdString viWidth ,VEConst s)] - else Right [(viWidth, Just (VEConst s))], + vi_inst_params = Right [(viWidth, VEConst s)], vi_inst_ports = zip muxInputs (map Just es) } @@ -986,9 +980,7 @@ vState flags rewire_map avinst = vminst = VMInst { vi_module_name = vIdV (vName vi), vi_inst_name = vInstId v_inst_name, - vi_inst_params = if ( vco_v95 vco ) - then Left (mapFst (Just . getVIdString) paramExprs) - else Right (mapSnd Just paramExprs), + vi_inst_params = Right paramExprs, vi_inst_ports = map (updateArgPosition ifc_position . tildeHack) args } @@ -1093,16 +1085,10 @@ aIds _ = internalError("Unexpected pattern in AVerilog::aIds" -- ============================== --- replace non v95 task with their name enclosed in a comment -vCommentTaskName :: VConvtOpts -> String -> String -vCommentTaskName vco s | vco_v95 vco && elem s (vco_v95_tasks vco) = " /*" ++ s ++ "*/ " - | otherwise = s - -- create a Verilog DPI/VPI task name from a foreign function name -- XXX When using DPI, if any types are poly, use the wrapper name vNameToTask :: Bool -> String -> String vNameToTask True s = s vNameToTask False s = "$imported_" ++ s - -- ============================== diff --git a/src/comp/Flags.hs b/src/comp/Flags.hs index 5ba682b58..771df1494 100644 --- a/src/comp/Flags.hs +++ b/src/comp/Flags.hs @@ -141,7 +141,6 @@ data Flags = Flags { usePrelude :: Bool, useProvisoSAT :: Bool, stdlibNames :: Bool, - v95 :: Bool, vFlags :: [String], vdir :: Maybe String, vPathRaw :: [String], diff --git a/src/comp/FlagsDecode.hs b/src/comp/FlagsDecode.hs index 61162eff5..774f4d88d 100644 --- a/src/comp/FlagsDecode.hs +++ b/src/comp/FlagsDecode.hs @@ -628,7 +628,6 @@ defaultFlags bluespecdir = Flags { usePrelude = True, useProvisoSAT = True, stdlibNames = False, - v95 = False, vFlags = [], vdir = Nothing, -- The vPath value will be produced from the raw value, @@ -1642,10 +1641,6 @@ externalFlags = [ (Toggle (\f x -> f {stdlibNames=x}) (showIfTrue stdlibNames), "the source file is from the standard library", Hidden)), - ("v95", - (Toggle (\f x -> f {v95=x}) (showIfTrue v95), - "generate strict Verilog 95 code", Visible)), - ("vdir", (Arg "dir" (\f s -> Left (f {vdir = Just s})) (Just (FRTMaybeString vdir)), "output directory for .v files", Visible)), @@ -1928,7 +1923,6 @@ showFlagsRaw flags = ("useNegate", show (useNegate flags)), ("usePrelude", show (usePrelude flags)), ("useProvisoSAT", show (useProvisoSAT flags)), - ("v95", show (v95 flags)), ("vFlags", show (vFlags flags)), ("vPath", show (vPath flags)), ("vPathRaw", show (vPathRaw flags)), diff --git a/src/comp/GenABin.hs b/src/comp/GenABin.hs index de7264716..b83612707 100644 --- a/src/comp/GenABin.hs +++ b/src/comp/GenABin.hs @@ -34,7 +34,7 @@ import qualified Data.ByteString as B -- .ba file tag -- change this whenever the .ba format changes -- See also GenBin.header header :: [Byte] -header = B.unpack $ TE.encodeUtf8 $ T.pack "bsc-ba-20230831-1" +header = B.unpack $ TE.encodeUtf8 $ T.pack "bsc-ba-20240718-1" genABinFile :: ErrorHandle -> String -> ABin -> IO () genABinFile errh fn abin = @@ -557,7 +557,7 @@ instance Bin Flags where a_100 a_101 a_102 a_103 a_104 a_105 a_106 a_107 a_108 a_109 a_110 a_111 a_112 a_113 a_114 a_115 a_116 a_117 a_118 a_119 a_120 a_121 a_122 a_123 a_124 a_125 a_126 a_127 a_128 a_129 - a_130 a_131 a_132 a_133) = + a_130 a_131 a_132) = do toBin a_000; toBin a_001; toBin a_002; toBin a_003; toBin a_004; toBin a_005; toBin a_006; toBin a_007; toBin a_008; toBin a_009; toBin a_010; toBin a_011; toBin a_012; toBin a_013; toBin a_014; @@ -584,7 +584,7 @@ instance Bin Flags where toBin a_115; toBin a_116; toBin a_117; toBin a_118; toBin a_119; toBin a_120; toBin a_121; toBin a_122; toBin a_123; toBin a_124; toBin a_125; toBin a_126; toBin a_127; toBin a_128; toBin a_129; - toBin a_130; toBin a_131; toBin a_132; toBin a_133 + toBin a_130; toBin a_131; toBin a_132; readBytes = do a_000 <- fromBin; a_001 <- fromBin; a_002 <- fromBin; a_003 <- fromBin; a_004 <- fromBin; a_005 <- fromBin; a_006 <- fromBin; a_007 <- fromBin; a_008 <- fromBin; a_009 <- fromBin; @@ -612,7 +612,7 @@ instance Bin Flags where a_115 <- fromBin; a_116 <- fromBin; a_117 <- fromBin; a_118 <- fromBin; a_119 <- fromBin; a_120 <- fromBin; a_121 <- fromBin; a_122 <- fromBin; a_123 <- fromBin; a_124 <- fromBin; a_125 <- fromBin; a_126 <- fromBin; a_127 <- fromBin; a_128 <- fromBin; a_129 <- fromBin; - a_130 <- fromBin; a_131 <- fromBin; a_132 <- fromBin; a_133 <- fromBin + a_130 <- fromBin; a_131 <- fromBin; a_132 <- fromBin; return (Flags a_000 a_001 a_002 a_003 a_004 a_005 a_006 a_007 a_008 a_009 a_010 a_011 a_012 a_013 a_014 a_015 a_016 a_017 a_018 a_019 @@ -627,7 +627,7 @@ instance Bin Flags where a_100 a_101 a_102 a_103 a_104 a_105 a_106 a_107 a_108 a_109 a_110 a_111 a_112 a_113 a_114 a_115 a_116 a_117 a_118 a_119 a_120 a_121 a_122 a_123 a_124 a_125 a_126 a_127 a_128 a_129 - a_130 a_131 a_132 a_133) + a_130 a_131 a_132) -- ---------- diff --git a/src/comp/GenBin.hs b/src/comp/GenBin.hs index cad48d9eb..0f5754c76 100644 --- a/src/comp/GenBin.hs +++ b/src/comp/GenBin.hs @@ -27,7 +27,7 @@ doTrace = elem "-trace-genbin" progArgs -- .bo file tag -- change this whenever the .bo format changes -- See also GenABin.header header :: [Byte] -header = B.unpack $ TE.encodeUtf8 $ T.pack "bsc-bo-20230831-1" +header = B.unpack $ TE.encodeUtf8 $ T.pack "bsc-bo-20240718-1" genBinFile :: ErrorHandle -> String -> CSignature -> CSignature -> IPackage a -> IO () diff --git a/src/comp/Verilog.hs b/src/comp/Verilog.hs index b315264ad..195421f18 100644 --- a/src/comp/Verilog.hs +++ b/src/comp/Verilog.hs @@ -286,7 +286,7 @@ data VMItem | VMInst { vi_module_name :: VId, vi_inst_name :: VId, -- The string is for comments - vi_inst_params :: Either [(Maybe String,VExpr)] [(VId, Maybe VExpr)], + vi_inst_params :: Either [VExpr] [(VId, VExpr)], vi_inst_ports :: [(VId, Maybe VExpr)] } | VMAssign VLValue VExpr | VMStmt { vi_translate_off :: Bool, vi_body :: VStmt } @@ -351,11 +351,11 @@ instance PPrint VMItem where pPrint d p (VMInst mid iid pvs cs) = pPrint d 0 mid <> (case pvs of Left ps -> (if null ps then text "" - else text " #" <> pparen True (sepList (map (pv95params d) ps) comma )) + else text " #" <> pparen True (sepList (map (pPrint d 0) ps) comma)) Right ps -> (if null ps then text "" else text " #" <> - pparen True (sepList (map (\ (i, me) -> text "." <> pPrint d 0 i <> - pparen True (case me of Just e -> pPrint d 0 e; Nothing -> text "")) ps) (text ",")))) <> + pparen True (sepList (map (\ (i, e) -> text "." <> pPrint d 0 i <> + pparen True (pPrint d 0 e)) ps) (text ",")))) <> text "" <+> pPrint d 0 iid <> pparen True (sepList (map (\ (i, me) -> text "." <> pPrint d 0 i <> pparen True (case me of @@ -376,11 +376,6 @@ instance PPrint VMItem where ppComment cs $+$ pPrint d p stmt -pv95params :: PDetail -> (Maybe String, VExpr) -> Doc -pv95params d (Nothing,x) = pPrint d 0 x -pv95params d (Just "", x) = pPrint d 0 x -pv95params d (Just s,x) = text (" /*" ++ s ++ "*/ ") <> pPrint d 0 x - -- Decide where to place blank spaces between VMItems, by grouping -- them into a list of lists between which there should be a space. -- A space is added around instantiations and statements (initial and diff --git a/testsuite/bsc.options/bsc.help.out.expected b/testsuite/bsc.options/bsc.help.out.expected index ffdc4ae8f..736c4b662 100644 --- a/testsuite/bsc.options/bsc.help.out.expected +++ b/testsuite/bsc.options/bsc.help.out.expected @@ -78,7 +78,6 @@ Compiler flags: -unspecified-to val remaining unspecified values are set to: 'X', '0', '1', 'Z', or 'A' -use-dpi use DPI instead of VPI in generated Verilog -v same as -verbose --v95 generate strict Verilog 95 code -vdir dir output directory for .v files -verbose be more talkative -verilog compile BSV generating Verilog file diff --git a/testsuite/bsc.options/bsc.print-flags-raw.out.expected b/testsuite/bsc.options/bsc.print-flags-raw.out.expected index c10db0cc6..46f28271e 100644 --- a/testsuite/bsc.options/bsc.print-flags-raw.out.expected +++ b/testsuite/bsc.options/bsc.print-flags-raw.out.expected @@ -120,7 +120,6 @@ Flags { useNegate = True, usePrelude = True, useProvisoSAT = True, - v95 = False, vFlags = [], vPath = [".","BLUESPECDIR/Libraries","BLUESPECDIR/Verilog"], vPathRaw = ["$DEFAULT_PATH"], diff --git a/testsuite/bsc.verilog/v95/Makefile b/testsuite/bsc.verilog/v95/Makefile deleted file mode 100644 index 48626d887..000000000 --- a/testsuite/bsc.verilog/v95/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# for "make clean" to work everywhere - -CONFDIR = $(realpath ../..) - -KEEPFILES = Param.v - -include $(CONFDIR)/clean.mk diff --git a/testsuite/bsc.verilog/v95/Param.v b/testsuite/bsc.verilog/v95/Param.v deleted file mode 100644 index ce14d0227..000000000 --- a/testsuite/bsc.verilog/v95/Param.v +++ /dev/null @@ -1,29 +0,0 @@ - -module Param ( CLK, - GO, - RDY_GO - ) ; - - // parameters are not in alphabetical or reverse order. - parameter C = 0 ; - parameter A = 0 ; - parameter B = 0 ; - - input CLK; - input GO; - output RDY_GO ; - - assign RDY_GO = 1'b1 ; - - always @ (posedge CLK ) - begin - if ( GO ) - begin - $display( "Parameter A is %d", A) ; - $display( "Parameter B is %d", B) ; - $display( "Parameter C is %d", C) ; - $finish(0); - end - end // always @ (posedge CLK ) - -endmodule // Param diff --git a/testsuite/bsc.verilog/v95/ParamOrder.bsv b/testsuite/bsc.verilog/v95/ParamOrder.bsv deleted file mode 100644 index b42938bc3..000000000 --- a/testsuite/bsc.verilog/v95/ParamOrder.bsv +++ /dev/null @@ -1,32 +0,0 @@ -package ParamOrder ; - -interface Ptest_Ifc; - method Action go() ; -endinterface - -import "BVI" Param = -module mkParam#(Integer a, Integer b, Integer c)( Ptest_Ifc) ; - - default_clock (CLK) ; - default_reset () ; - - // Parameter must be in same order as Verilog - parameter C = c; - parameter A = a; - parameter B = b; - - method go() enable(GO) ready(RDY_GO); - -endmodule - - -(* synthesize *) -module sysParamOrder() ; - Ptest_Ifc dut <- mkParam(1, 10 , 1000); - - rule fire ; - dut.go ; - endrule -endmodule - -endpackage diff --git a/testsuite/bsc.verilog/v95/Signed.bsv b/testsuite/bsc.verilog/v95/Signed.bsv deleted file mode 100644 index eada1ba65..000000000 --- a/testsuite/bsc.verilog/v95/Signed.bsv +++ /dev/null @@ -1,14 +0,0 @@ -// Test that the $signed functions are out of the generated code - -(* synthesize *) -module sysSigned() ; - - // Use signed data - Reg#(int) d <- mkReg(-4) ; - - rule check (True ) ; - d <= d + 1 ; - $display( "Showing signed data %0d", d ); - if ( d > 8 ) $finish(0) ; - endrule -endmodule diff --git a/testsuite/bsc.verilog/v95/sysParamOrder.out.expected b/testsuite/bsc.verilog/v95/sysParamOrder.out.expected deleted file mode 100644 index b06c09c0a..000000000 --- a/testsuite/bsc.verilog/v95/sysParamOrder.out.expected +++ /dev/null @@ -1,3 +0,0 @@ -Parameter A is 1 -Parameter B is 10 -Parameter C is 1000 diff --git a/testsuite/bsc.verilog/v95/sysSigned.out.expected b/testsuite/bsc.verilog/v95/sysSigned.out.expected deleted file mode 100644 index ee9aedf80..000000000 --- a/testsuite/bsc.verilog/v95/sysSigned.out.expected +++ /dev/null @@ -1,14 +0,0 @@ -Showing signed data -4 -Showing signed data -3 -Showing signed data -2 -Showing signed data -1 -Showing signed data 0 -Showing signed data 1 -Showing signed data 2 -Showing signed data 3 -Showing signed data 4 -Showing signed data 5 -Showing signed data 6 -Showing signed data 7 -Showing signed data 8 -Showing signed data 9 diff --git a/testsuite/bsc.verilog/v95/sysSigned.v95.out.expected b/testsuite/bsc.verilog/v95/sysSigned.v95.out.expected deleted file mode 100644 index a8a080685..000000000 --- a/testsuite/bsc.verilog/v95/sysSigned.v95.out.expected +++ /dev/null @@ -1,14 +0,0 @@ -Showing signed data 4294967292 -Showing signed data 4294967293 -Showing signed data 4294967294 -Showing signed data 4294967295 -Showing signed data 0 -Showing signed data 1 -Showing signed data 2 -Showing signed data 3 -Showing signed data 4 -Showing signed data 5 -Showing signed data 6 -Showing signed data 7 -Showing signed data 8 -Showing signed data 9 diff --git a/testsuite/bsc.verilog/v95/v95.exp b/testsuite/bsc.verilog/v95/v95.exp deleted file mode 100644 index b1270bdd1..000000000 --- a/testsuite/bsc.verilog/v95/v95.exp +++ /dev/null @@ -1,20 +0,0 @@ - -## Output should be the same regardless of v95 switch -test_veri_only_bsv_modules_options ParamOrder "" "" "" - -erase ParamOrder.bo -erase ParamOrder.bi -test_veri_only_bsv_modules_options ParamOrder "" "-v95" - -erase ParamOrder.bo -erase ParamOrder.bi -test_veri_only_bsv_modules_options ParamOrder "" "-no-v95" - - -test_veri_only_bsv_modules_options Signed "" "" -erase Signed.bo -erase Signed.bi -test_veri_only_bsv_modules_options Signed "" "-v95" "sysSigned.v95.out.expected" - - -