Add more tests

testsuite/bsc.verilog/splitports/ArgNamesPragma_PortNameConflict.bs

@@ -0,0 +1,25 @@
+package ArgNamesPragma_PortNameConflict where
+
+import SplitPorts
+import CShow
+
+struct Foo =
+  x :: Int 8
+  y :: Int 8
+  z :: Bool
+ deriving (Bits)
+
+instance SplitPorts Foo (Port (Int 8), Port (Int 8), Port Bool) where
+  splitPorts f = (Port f.x, Port f.y, Port f.z)
+  unsplitPorts (Port x, Port y, Port z) = Foo { x=x; y=y; z=z; }
+  portNames _ base = Cons (base +++ "_x") $ Cons (base +++ "_y") $ Cons (base +++ "_z") Nil
+
+interface SplitTest =
+  putFoo :: Foo -> Bool -> Action {-# prefix = "fooIn", arg_names = ["f", "f_z"] #-}
+
+{-# synthesize sysArgNamesPragma_PortNameConflict #-}
+sysArgNamesPragma_PortNameConflict :: Module SplitTest
+sysArgNamesPragma_PortNameConflict =
+  module
+    interface
+      putFoo x y = $display "putFoo: " (cshow x) (cshow y)

testsuite/bsc.verilog/splitports/ArgNamesPragma_PortNameConflict.bs.bsc-vcomp-out.expected

@@ -0,0 +1,7 @@
+checking package dependencies
+compiling ArgNamesPragma_PortNameConflict.bs
+code generation for sysArgNamesPragma_PortNameConflict starts
+Error: "ArgNamesPragma_PortNameConflict.bs", line 21, column 0: (G0055)
+  Method `putFoo' generates a port with name `fooIn_f_z' which conflicts with
+  a port of the same name generated by method `putFoo' at location
+  "ArgNamesPragma_PortNameConflict.bs", line 21, column 0.

testsuite/bsc.verilog/splitports/BadSplitInst_PortNameConflict.bs

@@ -0,0 +1,25 @@
+package BadSplitInst_PortNameConflict where
+
+import SplitPorts
+import CShow
+
+struct Foo =
+  x :: Int 8
+  y :: Int 8
+  z :: Bool
+ deriving (Bits)
+
+instance SplitPorts Foo (Port (Int 8), Port (Int 8), Port Bool) where
+  splitPorts f = (Port f.x, Port f.y, Port f.z)
+  unsplitPorts (Port x, Port y, Port z) = Foo { x=x; y=y; z=z; }
+  portNames _ base = Cons (base +++ "_x") $ Cons (base +++ "_y") $ Cons (base +++ "_x") Nil
+
+interface SplitTest =
+  putFoo :: Foo -> Action {-# prefix = "fooIn" #-}
+
+{-# synthesize sysBadSplitInst_PortNameConflict #-}
+sysBadSplitInst_PortNameConflict :: Module SplitTest
+sysBadSplitInst_PortNameConflict =
+  module
+    interface
+      putFoo x = $display "putFoo: " (cshow x)

testsuite/bsc.verilog/splitports/BadSplitInst_PortNameConflict.bs.bsc-vcomp-out.expected

@@ -0,0 +1,7 @@
+checking package dependencies
+compiling BadSplitInst_PortNameConflict.bs
+code generation for sysBadSplitInst_PortNameConflict starts
+Error: "BadSplitInst_PortNameConflict.bs", line 21, column 0: (G0055)
+  Method `putFoo' generates a port with name `fooIn_1_x' which conflicts with
+  a port of the same name generated by method `putFoo' at location
+  "BadSplitInst_PortNameConflict.bs", line 21, column 0.

testsuite/bsc.verilog/splitports/BadSplitInst_TooManyPortNames.bs

@@ -0,0 +1,24 @@
+package BadSplitInst_TooManyPortNames where
+
+import SplitPorts
+import CShow
+
+struct Foo =
+  x :: Int 8
+  y :: Int 8
+ deriving (Bits)
+
+instance SplitPorts Foo (Port (Int 8), Port (Int 8)) where
+  splitPorts f = (Port f.x, Port f.y)
+  unsplitPorts (Port x, Port y) = Foo { x=x; y=y; }
+  portNames _ base = Cons (base +++ "_x") $ Cons (base +++ "_y") $ Cons (base +++ "_z") Nil
+
+interface SplitTest =
+  putFoo :: Foo -> Action {-# prefix = "fooIn" #-}
+
+{-# synthesize sysBadSplitInst_TooManyPortNames #-}
+sysBadSplitInst_TooManyPortNames :: Module SplitTest
+sysBadSplitInst_TooManyPortNames =
+  module
+    interface
+      putFoo x = $display "putFoo: " (cshow x)

testsuite/bsc.verilog/splitports/BadSplitInst_TooManyPortNames.bs.bsc-vcomp-out.expected

@@ -0,0 +1,8 @@
+checking package dependencies
+compiling BadSplitInst_TooManyPortNames.bs
+code generation for sysBadSplitInst_TooManyPortNames starts
+Error: "Prelude.bs", line 4589, column 61: (S0015)
+  Bluespec evaluation-time error: SplitPorts: fooIn_1 has 2 ports, but 3 port
+  names were given
+  During elaboration of `sysBadSplitInst_TooManyPortNames' at
+  "BadSplitInst_TooManyPortNames.bs", line 20, column 0.

testsuite/bsc.verilog/splitports/PortNameConflict.bs

@@ -0,0 +1,34 @@
+package PortNameConflict where
+
+import SplitPorts
+import CShow
+
+struct Foo =
+  x :: Int 8
+  y :: Int 8
+ deriving (Bits)
+
+instance (ShallowSplitPorts Foo p) => SplitPorts Foo p where
+  splitPorts = shallowSplitPorts
+  unsplitPorts = shallowUnsplitPorts
+  portNames = shallowSplitPortNames
+
+struct Bar =
+  f :: Foo
+  f_x :: Int 16
+ deriving (Bits)
+
+instance (ShallowSplitPorts Bar p) => SplitPorts Bar p where
+  splitPorts = shallowSplitPorts
+  unsplitPorts = shallowUnsplitPorts
+  portNames = shallowSplitPortNames
+
+interface SplitTest =
+  putBar :: Bar -> Action {-# prefix = "barIn" #-}
+
+{-# synthesize sysPortNameConflict #-}
+sysPortNameConflict :: Module SplitTest
+sysPortNameConflict =
+  module
+    interface
+      putBar x = $display "putBar: " (cshow x)

testsuite/bsc.verilog/splitports/PortNameConflict.bs.bsc-vcomp-out.expected

@@ -0,0 +1,7 @@
+checking package dependencies
+compiling PortNameConflict.bs
+code generation for sysPortNameConflict starts
+Error: "PortNameConflict.bs", line 30, column 0: (G0055)
+  Method `putBar' generates a port with name `barIn_1_f_x' which conflicts
+  with a port of the same name generated by method `putBar' at location
+  "PortNameConflict.bs", line 30, column 0.

testsuite/bsc.verilog/splitports/SomeArgNames.bs

@@ -0,0 +1,46 @@
+package SomeArgNames where
+
+import SplitPorts
+import CShow
+
+struct Foo =
+  x :: Int 8
+  y :: Int 8
+ deriving (Bits)
+
+instance (ShallowSplitPorts Foo p) => SplitPorts Foo p where
+  splitPorts = shallowSplitPorts
+  unsplitPorts = shallowUnsplitPorts
+  portNames = shallowSplitPortNames
+
+struct Bar =
+  f :: Foo
+  b :: Bool
+ deriving (Bits)
+
+instance (ShallowSplitPorts Bar p) => SplitPorts Bar p where
+  splitPorts = shallowSplitPorts
+  unsplitPorts = shallowUnsplitPorts
+  portNames = shallowSplitPortNames
+
+interface SplitTest =
+  putFooBar :: Foo -> Bar -> Action {-# arg_names = ["fooIn"] #-}
+
+{-# synthesize mkSomeArgNamesSplitTest #-}
+mkSomeArgNamesSplitTest :: Module SplitTest
+mkSomeArgNamesSplitTest =
+  module
+    interface
+      putFooBar x y = $display "putFooBar: " (cshow x) "  " (cshow y)
+
+{-# synthesize sysSomeArgNames #-}
+sysSomeArgNames :: Module Empty
+sysSomeArgNames =
+  module
+    s <- mkSomeArgNamesSplitTest
+    i :: Reg (UInt 8) <- mkReg 0
+    rules
+      when True ==> i := i + 1
+      when i == 0 ==> s.putFooBar (Foo { x = 5; y = 6; }) (Bar { f = Foo { x = 7; y = 8; }; b = True; })
+      when i == 1 ==> $finish
+

testsuite/bsc.verilog/splitports/splitports.exp

@@ -37,4 +37,25 @@ if { $vtest == 1 } {
     find_regexp mkInstanceSplitTest.v {input  \[799 : 0\] putFoos_1;}
     find_regexp mkInstanceSplitTest.v {input  \[16 : 0\] putBaz_1_a;}
     find_regexp mkInstanceSplitTest.v {input  \[491 : 0\] putBaz_1_c;}
-}
+}
+
+test_c_veri SomeArgNames
+if { $vtest == 1 } {
+    find_regexp mkSomeArgNamesSplitTest.v {input  \[7 : 0\] putFooBar_fooIn_x;}
+    find_regexp mkSomeArgNamesSplitTest.v {input  \[7 : 0\] putFooBar_fooIn_y;}
+    find_regexp mkSomeArgNamesSplitTest.v {input  \[7 : 0\] putFooBar_2_f_x;}
+    find_regexp mkSomeArgNamesSplitTest.v {input  \[7 : 0\] putFooBar_2_f_y;}
+    find_regexp mkSomeArgNamesSplitTest.v {input  putFooBar_2_b;}
+}
+
+compile_verilog_fail_error PortNameConflict.bs G0055
+compare_file PortNameConflict.bs.bsc-vcomp-out
+
+compile_verilog_fail_error ArgNamesPragma_PortNameConflict.bs G0055
+compare_file ArgNamesPragma_PortNameConflict.bs.bsc-vcomp-out
+
+compile_verilog_fail_error BadSplitInst_PortNameConflict.bs G0055
+compare_file BadSplitInst_PortNameConflict.bs.bsc-vcomp-out
+
+compile_verilog_fail_error BadSplitInst_TooManyPortNames.bs S0015
+compare_file BadSplitInst_TooManyPortNames.bs.bsc-vcomp-out

testsuite/bsc.verilog/splitports/sysSomeArgNames.out.expected

@@ -0,0 +1 @@
+putFooBar: Foo {x=   5; y=   6}  Bar {f=Foo {x=   7; y=   8}; b=True}