A Verilog HDL project for CPU cores related to the original MOS 6502 CPU.

Have fun. 

The 65Org16-master branch is for a CPU core with:
  - 32-bit address space
    - by using 16-bit bytes
  - with no specific support for 8-bit bytes
  - with BCD mode as unspecified behaviour
  - and otherwise all opcodes and addressing modes like NMOS 6502

Please use other branches and add a suffix to your core name for
CPU cores with other goals.

Please note:

- The core has had next to no testing,

- There's an in-browser emulator at http://biged.github.com/6502js/

- Assembler support is catalogued at http://forum.6502.org/viewtopic.php?f=2&t=1851

- There are also verilog and support files here for a small system on
  FPGA, intended for xilinx spartan 3 as found on OHO GOP 24-pin module.
  The system has a uart module for communication to a host computer,
  which is implemented over i2c. The i2c module is not included for
  copyright reasons.  The system is absolutely minimal but is a work
  in progress,

- As a secondary goal it might be possible to configure the HDL as
  a 6502-compatible core with 8-bit bytes.

- LGPL license v2.1 is used for compatibility with opencores.org and to
  encourage redistribution of any source code improvements.
  (The license can be changed by agreement of all the copyright holders)

Notes on the cpu core:

- clk is active on the positive edge (is a phi1 clock)
- reset, IRQ and NMI are active high
- WE replaces, and is inverse sense of, read not write.
- databus has separate DI and DO
- RDY is not implemented
- external memory is assumed synchronous, so external pipelining is needed
- `define SIM for extra simulation instrumentation
- memory accesses may diverge from the original

Website for the original: http://ladybug.xs4all.nl/arlet/fpga/6502/

Note on licensing:

Relicensed to LGPL by kind permission of Arlet Ottens
"If you want to distribute it under the LGPL license that's fine with me"
16 May 2011 12:08