TimeSimpleCPU_stats.txt

---------- Begin Simulation Statistics ----------
final_tick                                  114677000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate                                 243112                       # Simulator instruction rate (inst/s)
host_mem_usage                                 663664                       # Number of bytes of host memory used
host_op_rate                                   281741                       # Simulator op (including micro ops) rate (op/s)
host_seconds                                     0.22                       # Real time elapsed on the host
host_tick_rate                              530215829                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                       52485                       # Number of instructions simulated
sim_ops                                         60928                       # Number of ops (including micro ops) simulated
sim_seconds                                  0.000115                       # Number of seconds simulated
sim_ticks                                   114677000                       # Number of ticks simulated
system.cpu.Branches                             10327                       # Number of branches fetched
system.cpu.committedInsts                       52485                       # Number of instructions committed
system.cpu.committedOps                         60928                       # Number of ops (including micro ops) committed
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.numCycles                           229354                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.num_busy_cycles               229353.998000                       # Number of busy cycles
system.cpu.num_cc_register_reads               213562                       # number of times the CC registers were read
system.cpu.num_cc_register_writes               32711                       # number of times the CC registers were written
system.cpu.num_conditional_control_insts         7566                       # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_func_calls                        1942                       # number of times a function call or return occured
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_int_alu_accesses                 52305                       # Number of integer alu accesses
system.cpu.num_int_insts                        52305                       # number of integer instructions
system.cpu.num_int_register_reads               84410                       # number of times the integer registers were read
system.cpu.num_int_register_writes              37597                       # number of times the integer registers were written
system.cpu.num_load_insts                       10196                       # Number of load instructions
system.cpu.num_mem_refs                         18867                       # number of memory refs
system.cpu.num_store_insts                       8671                       # Number of store instructions
system.cpu.num_vec_alu_accesses                     0                       # Number of vector alu accesses
system.cpu.num_vec_insts                            0                       # number of vector instructions
system.cpu.num_vec_register_reads                 392                       # number of times the vector registers were read
system.cpu.num_vec_register_writes                255                       # number of times the vector registers were written
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                     42123     68.42%     68.42% # Class of executed instruction
system.cpu.op_class::IntMult                      372      0.60%     69.03% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdDiv                        0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.03% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                  36      0.06%     69.09% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                  18      0.03%     69.11% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                  18      0.03%     69.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                129      0.21%     69.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdReduceAdd                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdReduceAlu                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdReduceCmp                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdFloatReduceAdd             0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdFloatReduceCmp             0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdAes                        0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdAesMix                     0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdSha1Hash                   0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdSha1Hash2                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdSha256Hash                 0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdSha256Hash2                0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdShaSigma2                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdShaSigma3                  0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::SimdPredAlu                    0      0.00%     69.35% # Class of executed instruction
system.cpu.op_class::MemRead                    10196     16.56%     85.92% # Class of executed instruction
system.cpu.op_class::MemWrite                    8671     14.08%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite                  0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                      61563                       # Class of executed instruction
system.cpu.workload.numSyscalls                    19                       # Number of system calls
system.membus.snoop_filter.hit_multi_requests            5                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_single_requests          195                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.tot_requests           855                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.clk_domain.clock                          1000                       # Clock period in ticks
system.cpu.dcache.demand_hits::.cpu.data        17988                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total            17988                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::.cpu.data        18065                       # number of overall hits
system.cpu.dcache.overall_hits::total           18065                       # number of overall hits
system.cpu.dcache.demand_misses::.cpu.data          187                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            187                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::.cpu.data          203                       # number of overall misses
system.cpu.dcache.overall_misses::total           203                       # number of overall misses
system.cpu.dcache.demand_miss_latency::.cpu.data     10966500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     10966500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::.cpu.data     10966500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     10966500                       # number of overall miss cycles
system.cpu.dcache.demand_accesses::.cpu.data        18175                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total        18175                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::.cpu.data        18268                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total        18268                       # number of overall (read+write) accesses
system.cpu.dcache.demand_miss_rate::.cpu.data     0.010289                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.010289                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::.cpu.data     0.011112                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.011112                       # miss rate for overall accesses
system.cpu.dcache.demand_avg_miss_latency::.cpu.data 58644.385027                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 58644.385027                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::.cpu.data 54022.167488                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54022.167488                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.demand_mshr_hits::.cpu.data            3                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total            3                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::.cpu.data            3                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total            3                       # number of overall MSHR hits
system.cpu.dcache.demand_mshr_misses::.cpu.data          184                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          184                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::.cpu.data          195                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          195                       # number of overall MSHR misses
system.cpu.dcache.demand_mshr_miss_latency::.cpu.data     10632500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     10632500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::.cpu.data     11238500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     11238500                       # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::.cpu.data     0.010124                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010124                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::.cpu.data     0.010674                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.010674                       # mshr miss rate for overall accesses
system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 57785.326087                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57785.326087                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 57633.333333                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57633.333333                       # average overall mshr miss latency
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.ReadReq_hits::.cpu.data         9952                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            9952                       # number of ReadReq hits
system.cpu.dcache.ReadReq_misses::.cpu.data          111                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           111                       # number of ReadReq misses
system.cpu.dcache.ReadReq_miss_latency::.cpu.data      6360500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      6360500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_accesses::.cpu.data        10063                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total        10063                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_rate::.cpu.data     0.011031                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011031                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 57301.801802                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 57301.801802                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_mshr_hits::.cpu.data            3                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::.cpu.data          108                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          108                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data      6102500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6102500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data     0.010732                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.010732                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 56504.629630                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56504.629630                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_hits::.cpu.data         8036                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           8036                       # number of WriteReq hits
system.cpu.dcache.WriteReq_misses::.cpu.data           76                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
system.cpu.dcache.WriteReq_miss_latency::.cpu.data      4606000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      4606000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_accesses::.cpu.data         8112                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         8112                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_miss_rate::.cpu.data     0.009369                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.009369                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 60605.263158                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60605.263158                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_mshr_misses::.cpu.data           76                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data      4530000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4530000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data     0.009369                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009369                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 59605.263158                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59605.263158                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_hits::.cpu.data           77                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total            77                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_misses::.cpu.data           16                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_accesses::.cpu.data           93                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total           93                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data     0.172043                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.172043                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data           11                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data       606000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       606000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data     0.118280                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.118280                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 55090.909091                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55090.909091                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits::.cpu.data          106                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total          106                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_accesses::.cpu.data          106                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total          106                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::.cpu.data          106                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total          106                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_accesses::.cpu.data          106                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total          106                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.tagsinuse           153.436862                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs               18472                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               195                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             94.728205                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle            148000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::.cpu.data   153.436862                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::.cpu.data     0.149841                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.149841                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          195                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           87                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.190430                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses             37155                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses            37155                       # Number of data accesses
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.instHits                             0                       # ITB inst hits
system.cpu.dtb.instMisses                           0                       # ITB inst misses
system.cpu.dtb.readHits                             0                       # DTB read hits
system.cpu.dtb.readMisses                           0                       # DTB read misses
system.cpu.dtb.writeHits                            0                       # DTB write hits
system.cpu.dtb.writeMisses                          0                       # DTB write misses
system.cpu.dtb.inserts                              0                       # Number of times an entry is inserted into the TLB
system.cpu.dtb.flushTlb                             0                       # Number of times complete TLB was flushed
system.cpu.dtb.flushTlbMva                          0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flushTlbMvaAsid                      0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flushTlbAsid                         0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flushedEntries                       0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.alignFaults                          0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetchFaults                       0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domainFaults                         0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.permsFaults                          0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.readAccesses                         0                       # DTB read accesses
system.cpu.dtb.writeAccesses                        0                       # DTB write accesses
system.cpu.dtb.instAccesses                         0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # Total TLB (inst and data) hits
system.cpu.dtb.misses                               0                       # Total TLB (inst and data) misses
system.cpu.dtb.accesses                             0                       # Total TLB (inst and data) accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.instHits            0                       # ITB inst hits
system.cpu.dtb.stage2_mmu.stage2_tlb.instMisses            0                       # ITB inst misses
system.cpu.dtb.stage2_mmu.stage2_tlb.readHits            0                       # DTB read hits
system.cpu.dtb.stage2_mmu.stage2_tlb.readMisses            0                       # DTB read misses
system.cpu.dtb.stage2_mmu.stage2_tlb.writeHits            0                       # DTB write hits
system.cpu.dtb.stage2_mmu.stage2_tlb.writeMisses            0                       # DTB write misses
system.cpu.dtb.stage2_mmu.stage2_tlb.inserts            0                       # Number of times an entry is inserted into the TLB
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlb            0                       # Number of times complete TLB was flushed
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlbMva            0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlbMvaAsid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlbAsid            0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.stage2_mmu.stage2_tlb.flushedEntries            0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.stage2_mmu.stage2_tlb.alignFaults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.prefetchFaults            0                       # Number of TLB faults due to prefetch
system.cpu.dtb.stage2_mmu.stage2_tlb.domainFaults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.permsFaults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.readAccesses            0                       # DTB read accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.writeAccesses            0                       # DTB write accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.instAccesses            0                       # ITB inst accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.hits            0                       # Total TLB (inst and data) hits
system.cpu.dtb.stage2_mmu.stage2_tlb.misses            0                       # Total TLB (inst and data) misses
system.cpu.dtb.stage2_mmu.stage2_tlb.accesses            0                       # Total TLB (inst and data) accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.demand_hits::.cpu.inst        61035                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total            61035                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::.cpu.inst        61035                       # number of overall hits
system.cpu.icache.overall_hits::total           61035                       # number of overall hits
system.cpu.icache.demand_misses::.cpu.inst          482                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            482                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::.cpu.inst          482                       # number of overall misses
system.cpu.icache.overall_misses::total           482                       # number of overall misses
system.cpu.icache.demand_miss_latency::.cpu.inst     23131000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     23131000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::.cpu.inst     23131000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     23131000                       # number of overall miss cycles
system.cpu.icache.demand_accesses::.cpu.inst        61517                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total        61517                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::.cpu.inst        61517                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total        61517                       # number of overall (read+write) accesses
system.cpu.icache.demand_miss_rate::.cpu.inst     0.007835                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.007835                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::.cpu.inst     0.007835                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.007835                       # miss rate for overall accesses
system.cpu.icache.demand_avg_miss_latency::.cpu.inst 47989.626556                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 47989.626556                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::.cpu.inst 47989.626556                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 47989.626556                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::.writebacks          178                       # number of writebacks
system.cpu.icache.writebacks::total               178                       # number of writebacks
system.cpu.icache.demand_mshr_misses::.cpu.inst          482                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          482                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::.cpu.inst          482                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          482                       # number of overall MSHR misses
system.cpu.icache.demand_mshr_miss_latency::.cpu.inst     22649000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     22649000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::.cpu.inst     22649000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     22649000                       # number of overall MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::.cpu.inst     0.007835                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.007835                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::.cpu.inst     0.007835                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.007835                       # mshr miss rate for overall accesses
system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 46989.626556                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 46989.626556                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 46989.626556                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 46989.626556                       # average overall mshr miss latency
system.cpu.icache.replacements                    178                       # number of replacements
system.cpu.icache.ReadReq_hits::.cpu.inst        61035                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total           61035                       # number of ReadReq hits
system.cpu.icache.ReadReq_misses::.cpu.inst          482                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           482                       # number of ReadReq misses
system.cpu.icache.ReadReq_miss_latency::.cpu.inst     23131000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     23131000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses::.cpu.inst        61517                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total        61517                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_miss_rate::.cpu.inst     0.007835                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.007835                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 47989.626556                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 47989.626556                       # average ReadReq miss latency
system.cpu.icache.ReadReq_mshr_misses::.cpu.inst          482                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          482                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst     22649000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     22649000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst     0.007835                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007835                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 46989.626556                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46989.626556                       # average ReadReq mshr miss latency
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.tagsinuse           229.012968                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs               61517                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               482                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            127.628631                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle             77000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::.cpu.inst   229.012968                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::.cpu.inst     0.447291                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.447291                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          304                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           73                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.593750                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses            123516                       # Number of tag accesses
system.cpu.icache.tags.data_accesses           123516                       # Number of data accesses
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.instHits                             0                       # ITB inst hits
system.cpu.itb.instMisses                           0                       # ITB inst misses
system.cpu.itb.readHits                             0                       # DTB read hits
system.cpu.itb.readMisses                           0                       # DTB read misses
system.cpu.itb.writeHits                            0                       # DTB write hits
system.cpu.itb.writeMisses                          0                       # DTB write misses
system.cpu.itb.inserts                              0                       # Number of times an entry is inserted into the TLB
system.cpu.itb.flushTlb                             0                       # Number of times complete TLB was flushed
system.cpu.itb.flushTlbMva                          0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flushTlbMvaAsid                      0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flushTlbAsid                         0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flushedEntries                       0                       # Number of entries that have been flushed from TLB
system.cpu.itb.alignFaults                          0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetchFaults                       0                       # Number of TLB faults due to prefetch
system.cpu.itb.domainFaults                         0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.permsFaults                          0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.readAccesses                         0                       # DTB read accesses
system.cpu.itb.writeAccesses                        0                       # DTB write accesses
system.cpu.itb.instAccesses                         0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # Total TLB (inst and data) hits
system.cpu.itb.misses                               0                       # Total TLB (inst and data) misses
system.cpu.itb.accesses                             0                       # Total TLB (inst and data) accesses
system.cpu.itb.stage2_mmu.stage2_tlb.instHits            0                       # ITB inst hits
system.cpu.itb.stage2_mmu.stage2_tlb.instMisses            0                       # ITB inst misses
system.cpu.itb.stage2_mmu.stage2_tlb.readHits            0                       # DTB read hits
system.cpu.itb.stage2_mmu.stage2_tlb.readMisses            0                       # DTB read misses
system.cpu.itb.stage2_mmu.stage2_tlb.writeHits            0                       # DTB write hits
system.cpu.itb.stage2_mmu.stage2_tlb.writeMisses            0                       # DTB write misses
system.cpu.itb.stage2_mmu.stage2_tlb.inserts            0                       # Number of times an entry is inserted into the TLB
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlb            0                       # Number of times complete TLB was flushed
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlbMva            0                       # Number of times TLB was flushed by MVA
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlbMvaAsid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlbAsid            0                       # Number of times TLB was flushed by ASID
system.cpu.itb.stage2_mmu.stage2_tlb.flushedEntries            0                       # Number of entries that have been flushed from TLB
system.cpu.itb.stage2_mmu.stage2_tlb.alignFaults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.prefetchFaults            0                       # Number of TLB faults due to prefetch
system.cpu.itb.stage2_mmu.stage2_tlb.domainFaults            0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.permsFaults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.readAccesses            0                       # DTB read accesses
system.cpu.itb.stage2_mmu.stage2_tlb.writeAccesses            0                       # DTB write accesses
system.cpu.itb.stage2_mmu.stage2_tlb.instAccesses            0                       # ITB inst accesses
system.cpu.itb.stage2_mmu.stage2_tlb.hits            0                       # Total TLB (inst and data) hits
system.cpu.itb.stage2_mmu.stage2_tlb.misses            0                       # Total TLB (inst and data) misses
system.cpu.itb.stage2_mmu.stage2_tlb.accesses            0                       # Total TLB (inst and data) accesses
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.power_state.pwrStateResidencyTicks::ON    114677000                       # Cumulative time (in ticks) in various power states
system.cpu.thread_0.numInsts                        0                       # Number of Instructions committed
system.cpu.thread_0.numOps                          0                       # Number of Ops committed
system.cpu.thread_0.numMemRefs                      0                       # Number of Memory References
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts
system.mem_ctrls.avgPriority_.writebacks::samples        58.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_.cpu.inst::samples       357.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_.cpu.data::samples       194.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.priorityMinLatency      0.000000018750                       # per QoS priority minimum request to response latency (s)
system.mem_ctrls.priorityMaxLatency      0.000172406500                       # per QoS priority maximum request to response latency (s)
system.mem_ctrls.numReadWriteTurnArounds            2                       # Number of turnarounds from READ to WRITE
system.mem_ctrls.numWriteReadTurnArounds            2                       # Number of turnarounds from WRITE to READ
system.mem_ctrls.numStayReadState                1301                       # Number of times bus staying in READ state
system.mem_ctrls.numStayWriteState                 32                       # Number of times bus staying in WRITE state
system.mem_ctrls.readReqs                         677                       # Number of read requests accepted
system.mem_ctrls.writeReqs                        173                       # Number of write requests accepted
system.mem_ctrls.readBursts                       677                       # Number of controller read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                      173                       # Number of controller write bursts, including those merged in the write queue
system.mem_ctrls.servicedByWrQ                    126                       # Number of controller read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                   115                       # Number of controller write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                      17.98                       # Average write queue length when enqueuing
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                   677                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                  173                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                     547                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                       4                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.rdPerTurnAround::samples            2                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean            264                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean    134.785014                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev    321.026479                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::32-47             1     50.00%     50.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::480-495            1     50.00%    100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total             2                       # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples            2                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean             17                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean     16.970563                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev      1.414214                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16                1     50.00%     50.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18                1     50.00%    100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total             2                       # Writes before turning the bus around for reads
system.mem_ctrls.bytesReadWrQ                    8064                       # Total number of bytes read from write queue
system.mem_ctrls.bytesReadSys                   43328                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys                11072                       # Total written bytes from the system interface side
system.mem_ctrls.avgRdBWSys                    377.83                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                     96.55                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.totGap                     114663000                       # Total gap between requests
system.mem_ctrls.avgGap                     134897.65                       # Average gap between requests
system.mem_ctrls.requestorReadBytes::.cpu.inst        22848                       # Per-requestor bytes read from memory
system.mem_ctrls.requestorReadBytes::.cpu.data        12416                       # Per-requestor bytes read from memory
system.mem_ctrls.requestorWriteBytes::.writebacks         2176                       # Per-requestor bytes write to memory
system.mem_ctrls.requestorReadRate::.cpu.inst 199237859.378951311111                       # Per-requestor bytes read from memory rate (Bytes/sec)
system.mem_ctrls.requestorReadRate::.cpu.data 108269312.939822286367                       # Per-requestor bytes read from memory rate (Bytes/sec)
system.mem_ctrls.requestorWriteRate::.writebacks 18975034.226566791534                       # Per-requestor bytes write to memory rate (Bytes/sec)
system.mem_ctrls.requestorReadAccesses::.cpu.inst          482                       # Per-requestor read serviced memory accesses
system.mem_ctrls.requestorReadAccesses::.cpu.data          195                       # Per-requestor read serviced memory accesses
system.mem_ctrls.requestorWriteAccesses::.writebacks          173                       # Per-requestor write serviced memory accesses
system.mem_ctrls.requestorReadTotalLat::.cpu.inst      8800500                       # Per-requestor read total memory access latency
system.mem_ctrls.requestorReadTotalLat::.cpu.data      5116500                       # Per-requestor read total memory access latency
system.mem_ctrls.requestorWriteTotalLat::.writebacks   1081727750                       # Per-requestor write total memory access latency
system.mem_ctrls.requestorReadAvgLat::.cpu.inst     18258.30                       # Per-requestor read average memory access latency
system.mem_ctrls.requestorReadAvgLat::.cpu.data     26238.46                       # Per-requestor read average memory access latency
system.mem_ctrls.requestorWriteAvgLat::.writebacks   6252761.56                       # Per-requestor write average memory access latency
system.mem_ctrls.dram.bytes_read::.cpu.inst        30848                       # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::.cpu.data        12480                       # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::total         43328                       # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_inst_read::.cpu.inst        30848                       # Number of instructions bytes read from this memory
system.mem_ctrls.dram.bytes_inst_read::total        30848                       # Number of instructions bytes read from this memory
system.mem_ctrls.dram.num_reads::.cpu.inst          482                       # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::.cpu.data          195                       # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::total            677                       # Number of read requests responded to by this memory
system.mem_ctrls.dram.bw_read::.cpu.inst    268999015                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::.cpu.data    108827402                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::total        377826417                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_inst_read::.cpu.inst    268999015                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_inst_read::total    268999015                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu.inst    268999015                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu.data    108827402                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::total       377826417                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.readBursts                  551                       # Number of DRAM read bursts
system.mem_ctrls.dram.writeBursts                  34                       # Number of DRAM write bursts
system.mem_ctrls.dram.perBankRdBursts::0           54                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::1           55                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::2           21                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::3           22                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::4           13                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::5           22                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::6           46                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::7           33                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::8           47                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::9           83                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::10           54                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::11           58                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::12           19                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::13           11                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::14           11                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::15            2                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::0            8                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::1            5                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::2            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::3            2                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::4            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::5            3                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::6            3                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::7            6                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::8            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::9            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::10            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::11            3                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::12            4                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::13            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::14            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::15            0                       # Per bank write bursts
system.mem_ctrls.dram.totQLat                 3585750                       # Total ticks spent queuing
system.mem_ctrls.dram.totBusLat               2755000                       # Total ticks spent in databus transfers
system.mem_ctrls.dram.totMemAccLat           13917000                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.dram.avgQLat                 6507.71                       # Average queueing delay per DRAM burst
system.mem_ctrls.dram.avgBusLat               5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.dram.avgMemAccLat           25257.71                       # Average memory access latency per DRAM burst
system.mem_ctrls.dram.readRowHits                 423                       # Number of row buffer hits during reads
system.mem_ctrls.dram.writeRowHits                 22                       # Number of row buffer hits during writes
system.mem_ctrls.dram.readRowHitRate            76.77                       # Row buffer hit rate for reads
system.mem_ctrls.dram.writeRowHitRate           64.71                       # Row buffer hit rate for writes
system.mem_ctrls.dram.bytesPerActivate::samples          128                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::mean          276                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::gmean   182.842070                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::stdev   277.723932                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::0-127           38     29.69%     29.69% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::128-255           39     30.47%     60.16% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::256-383           23     17.97%     78.12% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::384-511           10      7.81%     85.94% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::512-639            1      0.78%     86.72% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::640-767            3      2.34%     89.06% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::768-895            3      2.34%     91.41% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::896-1023            2      1.56%     92.97% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::1024-1151            9      7.03%    100.00% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::total          128                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesRead                 35264                       # Total number of bytes read from DRAM
system.mem_ctrls.dram.bytesWritten               2176                       # Total number of bytes written to DRAM
system.mem_ctrls.dram.avgRdBW              307.507172                       # Average DRAM read bandwidth in MiBytes/s
system.mem_ctrls.dram.avgWrBW               18.975034                       # Average DRAM write bandwidth in MiBytes/s
system.mem_ctrls.dram.peakBW                 12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.dram.busUtil                    2.55                       # Data bus utilization in percentage
system.mem_ctrls.dram.busUtilRead                2.40                       # Data bus utilization in percentage for reads
system.mem_ctrls.dram.busUtilWrite               0.15                       # Data bus utilization in percentage for writes
system.mem_ctrls.dram.pageHitRate               76.07                       # Row buffer hit rate, read and write combined
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.mem_ctrls.dram.rank0.actEnergy          449820                       # Energy for activate commands per rank (pJ)
system.mem_ctrls.dram.rank0.preEnergy          216315                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls.dram.rank0.readEnergy        1899240                       # Energy for read commands per rank (pJ)
system.mem_ctrls.dram.rank0.writeEnergy        140940                       # Energy for write commands per rank (pJ)
system.mem_ctrls.dram.rank0.refreshEnergy 8604960.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls.dram.rank0.actBackEnergy     31843620                       # Energy for active background per rank (pJ)
system.mem_ctrls.dram.rank0.preBackEnergy     17220480                       # Energy for precharge background per rank (pJ)
system.mem_ctrls.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ)
system.mem_ctrls.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ)
system.mem_ctrls.dram.rank0.totalEnergy      60375375                       # Total energy per rank (pJ)
system.mem_ctrls.dram.rank0.averagePower   526.481989                       # Core power per rank (mW)
system.mem_ctrls.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE     44510000                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::REF      3640000                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::ACT     66527000                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls.dram.rank1.actEnergy          549780                       # Energy for activate commands per rank (pJ)
system.mem_ctrls.dram.rank1.preEnergy          269445                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls.dram.rank1.readEnergy        2034900                       # Energy for read commands per rank (pJ)
system.mem_ctrls.dram.rank1.writeEnergy         36540                       # Energy for write commands per rank (pJ)
system.mem_ctrls.dram.rank1.refreshEnergy 8604960.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls.dram.rank1.actBackEnergy     23657850                       # Energy for active background per rank (pJ)
system.mem_ctrls.dram.rank1.preBackEnergy     24113760                       # Energy for precharge background per rank (pJ)
system.mem_ctrls.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ)
system.mem_ctrls.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ)
system.mem_ctrls.dram.rank1.totalEnergy      59267235                       # Total energy per rank (pJ)
system.mem_ctrls.dram.rank1.averagePower   516.818848                       # Core power per rank (mW)
system.mem_ctrls.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE     62492750                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::REF      3640000                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::ACT     48544250                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                601                       # Transaction distribution
system.membus.trans_dist::WritebackClean          178                       # Transaction distribution
system.membus.trans_dist::ReadExReq                76                       # Transaction distribution
system.membus.trans_dist::ReadExResp               76                       # Transaction distribution
system.membus.trans_dist::ReadCleanReq            482                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           119                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache.mem_side_port::system.mem_ctrls.port         1142                       # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count_system.cpu.dcache.mem_side_port::system.mem_ctrls.port          390                       # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count::total                   1532                       # Packet count per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu.icache.mem_side_port::system.mem_ctrls.port        42240                       # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu.dcache.mem_side_port::system.mem_ctrls.port        12480                       # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size::total                   54720                       # Cumulative packet size per connected requestor and responder (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               677                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.032496                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.177445                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     655     96.75%     96.75% # Request fanout histogram
system.membus.snoop_fanout::1                      22      3.25%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total                 677                       # Request fanout histogram
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED    114677000                       # Cumulative time (in ticks) in various power states
system.membus.reqLayer0.occupancy             1591500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2525500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy            1040750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.9                       # Layer utilization (%)
system.voltage_domain.voltage                       1                       # Voltage in Volts

---------- End Simulation Statistics   ----------