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squash stm32g4
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bkleiner committed May 8, 2024
1 parent 6b1abdc commit 7563530
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Showing 4 changed files with 6 additions and 5 deletions.
2 changes: 1 addition & 1 deletion src/driver/adc.c
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ uint16_t adc_array[ADC_CHAN_MAX];
adc_channel_t adc_pins[ADC_CHAN_MAX];

extern uint16_t adc_read_raw(adc_chan_t index);
extern float adc_convert_to_temp(float val);
extern float adc_convert_to_temp(uint16_t val);

static float adc_convert_to_mv(float value) {
const float vref = (float)(VREFINT_CAL * VREFINT_CAL_VREF) / (float)adc_read_raw(ADC_CHAN_VREF);
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2 changes: 1 addition & 1 deletion src/driver/at32/adc.c
Original file line number Diff line number Diff line change
Expand Up @@ -149,6 +149,6 @@ uint16_t adc_read_raw(adc_chan_t index) {
return adc_array[index];
}

float adc_convert_to_temp(float val) {
float adc_convert_to_temp(uint16_t val) {
return (ADC_TEMP_BASE - val * ADC_VREF / 4096) / ADC_TEMP_SLOPE + 25;
}
3 changes: 2 additions & 1 deletion src/driver/stm32/adc.c
Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ static void adc_init_dev(adc_devices_t index) {
LL_ADC_EnableInternalRegulator(dev->adc);
time_delay_us(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);

LL_ADC_StartCalibration(dev->adc, LL_ADC_SINGLE_ENDED);
while (LL_ADC_IsCalibrationOnGoing(dev->adc) != 0)
;

Expand Down Expand Up @@ -238,7 +239,7 @@ uint16_t adc_read_raw(adc_chan_t index) {
return adc_array[index];
}

float adc_convert_to_temp(float val) {
float adc_convert_to_temp(uint16_t val) {
#ifdef STM32H7
// adc cal is 16bit on h7, shift by 4bit left
val *= 16;
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4 changes: 2 additions & 2 deletions src/system/stm32g473/system.c
Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ static void SystemClock_Config(void) {
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
RCC_OscInitStruct.PLL.PLLN = 21;
RCC_OscInitStruct.PLL.PLLN = 42;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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