From 428500db31bbdf0961794fcf57505e9d54f77686 Mon Sep 17 00:00:00 2001 From: Broderick Carlin Date: Sun, 26 Nov 2023 19:50:04 -0600 Subject: [PATCH] refactor: Pull in maybe_async crate to remove a lot of duplicate code --- Cargo.toml | 3 +- src/lib.rs | 96 ++++++++++++------------------------------------------ 2 files changed, 22 insertions(+), 77 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 5fe3240..08ea924 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -18,8 +18,9 @@ version = "0.1.0" defmt = "0.3" embedded-hal = { version = "1.0.0-rc.1", optional = true } embedded-hal-async = { version = "1.0.0-rc.1", optional = true } +maybe-async = "0.2" [features] default = ["blocking"] async = ["embedded-hal-async"] -blocking = ["embedded-hal"] \ No newline at end of file +blocking = ["embedded-hal", "maybe-async/is_sync"] diff --git a/src/lib.rs b/src/lib.rs index 283041d..861d887 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -4,6 +4,11 @@ use commands::{Command, Mode}; pub use error::*; use registers::{ReadableRegister, WritableRegister}; +#[cfg(feature = "blocking")] +use embedded_hal::spi::{Operation, SpiDevice}; +#[cfg(feature = "async")] +use embedded_hal_async::spi::{Operation, SpiDevice}; + pub mod commands; mod error; pub mod registers; @@ -28,107 +33,44 @@ impl A7105 { } } -#[cfg(feature = "blocking")] -impl A7105 { - /// Reads a value from a regsiter, determined by the specified return type. - pub fn read_reg>(&mut self) -> Result { - let mut buf = [0u8; N]; - self.spi.transaction(&mut [ - embedded_hal::spi::Operation::Write(&[R::id() | Self::READ_FLAG]), - embedded_hal::spi::Operation::Read(&mut buf), - ])?; - Ok(R::from_slice(buf)) - } - - /// Writes a value to a regsiter, determined by the specified register type. - pub fn write_reg>( - &mut self, - reg: R, - ) -> Result<(), SPI::Error> { - self.spi.transaction(&mut [ - embedded_hal::spi::Operation::Write(&[R::id()]), - embedded_hal::spi::Operation::Write(®.into_slice()), - ]) - } - - /// Sets the A7105 into the specified mode - pub fn set_mode(&mut self, mode: Mode) -> Result<(), SPI::Error> { - self.spi.write(&[mode.into()]) - } - - /// Issues the given command to the A7105 - pub fn command(&mut self, command: Command) -> Result<(), SPI::Error> { - let buf: &[u8] = match command { - Command::Reset => &[0x00, 0x00], - Command::ResetFifoReadPointer => &[0b1111_0000], - Command::ResetFifoWritePointer => &[0b1110_0000], - }; - self.spi.write(buf) - } - - /// Attempts to read a recieved packet from the A7105's internal RX buffer - pub fn rx_packet(&mut self, buf: &mut [u8]) -> Result<(), ReadPacketError> { - // Start by verifying that the packet we received is actaully valid - let mode: registers::Mode = self.read_reg()?; - if !mode.crc_pass || !mode.fec_pass { - // The packet we got was invalid, so there isn't anything to read - return Err(ReadPacketError::PacketError(mode.into())); - } - - // The packet was valid so reset the read pointer and do the actual read - self.command(Command::ResetFifoReadPointer)?; - self.spi.transaction(&mut [ - embedded_hal::spi::Operation::Write(&[Self::RX_BUFFER_ID | Self::READ_FLAG]), - embedded_hal::spi::Operation::Read(buf), - ])?; - Ok(()) - } - - /// Attempts to write a packet to the A7105's internal TX buffer - pub fn tx_packet(&mut self, buf: &[u8]) -> Result<(), SPI::Error> { - self.command(Command::ResetFifoWritePointer)?; - self.spi.transaction(&mut [ - embedded_hal::spi::Operation::Write(&[Self::TX_BUFFER_ID]), - embedded_hal::spi::Operation::Write(buf), - ]) - } -} - -#[cfg(feature = "async")] -impl A7105 { +impl A7105 { /// Reads a value from a regsiter, determined by the specified return type. + #[maybe_async::maybe_async] pub async fn read_reg>( &mut self, ) -> Result { let mut buf = [0u8; N]; self.spi .transaction(&mut [ - embedded_hal_async::spi::Operation::Write(&[R::id() | Self::READ_FLAG]), - embedded_hal_async::spi::Operation::Read(&mut buf), + Operation::Write(&[R::id() | Self::READ_FLAG]), + Operation::Read(&mut buf), ]) .await?; Ok(R::from_slice(buf)) } /// Writes a value to a regsiter, determined by the specified register type. + #[maybe_async::maybe_async] pub async fn write_reg( &mut self, reg: R, ) -> Result<(), SPI::Error> { self.spi .transaction(&mut [ - embedded_hal_async::spi::Operation::Write(&[R::id()]), - embedded_hal_async::spi::Operation::Write(®.into_slice()), + Operation::Write(&[R::id()]), + Operation::Write(®.into_slice()), ]) .await } /// Sets the A7105 into the specified mode + #[maybe_async::maybe_async] pub async fn set_mode(&mut self, mode: Mode) -> Result<(), SPI::Error> { self.spi.write(&[mode.into()]).await } /// Issues the given command to the A7105 + #[maybe_async::maybe_async] pub async fn command(&mut self, command: Command) -> Result<(), SPI::Error> { let buf: &[u8] = match command { Command::Reset => &[0x00, 0x00], @@ -139,6 +81,7 @@ impl A7105 { } /// Attempts to read a recieved packet from the A7105's internal RX buffer + #[maybe_async::maybe_async] pub async fn rx_packet(&mut self, buf: &mut [u8]) -> Result<(), ReadPacketError> { // Start by verifying that the packet we received is actaully valid let mode: registers::Mode = self.read_reg().await?; @@ -151,20 +94,21 @@ impl A7105 { self.command(Command::ResetFifoReadPointer).await?; self.spi .transaction(&mut [ - embedded_hal_async::spi::Operation::Write(&[Self::RX_BUFFER_ID | Self::READ_FLAG]), - embedded_hal_async::spi::Operation::Read(buf), + Operation::Write(&[Self::RX_BUFFER_ID | Self::READ_FLAG]), + Operation::Read(buf), ]) .await?; Ok(()) } /// Attempts to write a packet to the A7105's internal TX buffer + #[maybe_async::maybe_async] pub async fn tx_packet(&mut self, buf: &[u8]) -> Result<(), SPI::Error> { self.command(Command::ResetFifoWritePointer).await?; self.spi .transaction(&mut [ - embedded_hal_async::spi::Operation::Write(&[Self::TX_BUFFER_ID]), - embedded_hal_async::spi::Operation::Write(buf), + Operation::Write(&[Self::TX_BUFFER_ID]), + Operation::Write(buf), ]) .await }