feat: refactor Instruction and multicore

Cargo.toml

@@ -10,15 +10,13 @@ repository = "https://github.com/Byte-OS/polyhal"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [features]
-kcontext = []
-multicore = ["boot"]
 trap = []
 boot = []
 logger = []
 
 graphic = []
 
-default = ["boot", "kcontext"]
+default = ["boot"]
 
 [dependencies]
 log = "0.4"

example/Cargo.toml

@@ -11,8 +11,7 @@ polyhal = { version = "0.1.2", features = [
   "logger",
   "boot",
   "trap",
-  "graphic",
-  "multicore"
+  "graphic"
 ] }
 log = "0.4"
 fdt = "0.1.5"

example/src/frame.rs

@@ -11,10 +11,10 @@ pub fn add_frame_range(mm_start: usize, mm_end: usize) {
     LOCK_FRAME_ALLOCATOR.lock().add_frame(start, end);
 }
 
-pub fn frame_alloc() -> PhysPage {
+pub fn frame_alloc(count: usize) -> PhysPage {
     let ppn = LOCK_FRAME_ALLOCATOR
         .lock()
-        .alloc(1)
+        .alloc(count)
         .expect("can't find memory page");
     PhysPage::new(ppn)
 }

example/src/main.rs

@@ -11,16 +11,19 @@ use core::panic::PanicInfo;
 use frame::frame_alloc;
 use polyhal::addr::PhysPage;
 use polyhal::common::{get_mem_areas, PageAlloc};
+use polyhal::consts::VIRT_ADDR_START;
 use polyhal::debug_console::DebugConsole;
-use polyhal::instruction::Instruction;
+use polyhal::instruction::{ebreak, shutdown};
+use polyhal::multicore::boot_core;
+use polyhal::pagetable::PAGE_SIZE;
 use polyhal::trap::TrapType::{self, *};
-use polyhal::trapframe::TrapFrame;
+use polyhal::trapframe::{TrapFrame, TrapFrameArgs};
 
 pub struct PageAllocImpl;
 
 impl PageAlloc for PageAllocImpl {
     fn alloc(&self) -> PhysPage {
-        frame_alloc()
+        frame_alloc(1)
     }
 
     fn dealloc(&self, ppn: PhysPage) {
@@ -33,7 +36,9 @@ impl PageAlloc for PageAllocImpl {
 fn kernel_interrupt(ctx: &mut TrapFrame, trap_type: TrapType) {
     // println!("trap_type @ {:x?} {:#x?}", trap_type, ctx);
     match trap_type {
-        Breakpoint => return,
+        Breakpoint => {
+            log::info!("@BP @ {:#x}", ctx[TrapFrameArgs::SEPC]);
+        }
         SysCall => {
             // jump to next instruction anyway
             ctx.syscall_ok();
@@ -77,11 +82,15 @@ fn main(hartid: usize) {
 
     get_mem_areas().into_iter().for_each(|(start, size)| {
         println!("init memory region {:#x} - {:#x}", start, start + size);
-        // frame::add_frame_range(start, start + size);
+        frame::add_frame_range(start, start + size);
     });
 
-    polyhal::multicore::MultiCore::boot_all();
+    // Boot another core that id is 1.
+    let sp = frame_alloc(16);
+    boot_core(1, (sp.to_addr() | VIRT_ADDR_START) + 16 * PAGE_SIZE);
 
+    // Test BreakPoint
+    ebreak();
 
     crate::pci::init();
 
@@ -92,7 +101,7 @@ fn main(hartid: usize) {
     }
 
     log::info!("Run END. Shutdown successfully.");
-    Instruction::shutdown();
+    shutdown();
 }
 
 #[panic_handler]
@@ -107,5 +116,5 @@ fn panic(info: &PanicInfo) -> ! {
     } else {
         log::error!("[kernel] Panicked: {}", info.message().unwrap());
     }
-    Instruction::shutdown()
+    shutdown()
 }

src/components/boot/aarch64.rs

@@ -5,16 +5,16 @@ use fdt::Fdt;
 use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
 
 use crate::{
-    clear_bss,
     components::{
         common::{CPU_NUM, DTB_PTR},
         consts::VIRT_ADDR_START,
         debug_console::{display_info, println},
-        instruction::Instruction,
+        instruction,
         pagetable::{PTEFlags, TLB},
         percpu::percpu_area_init,
         timer,
     },
+    multicore::CpuCore,
     pagetable::PTE,
     PageTable, PhysPage,
 };
@@ -166,9 +166,10 @@ unsafe extern "C" fn _secondary_boot() -> ! {
 }
 
 pub fn rust_tmp_main(hart_id: usize, device_tree: usize) {
-    clear_bss();
+    super::clear_bss();
     percpu_area_init(hart_id);
-    // pl011::init_early();
+    CpuCore::init(hart_id);
+
     // Init DebugConsole early.
     crate::components::debug_console::init_early();
     #[cfg(feature = "logger")]
@@ -215,7 +216,7 @@ pub fn rust_tmp_main(hart_id: usize, device_tree: usize) {
     // Enter to kernel entry point(`main` function).
     unsafe { crate::components::boot::_main_for_arch(hart_id) };
 
-    Instruction::shutdown();
+    instruction::shutdown();
 }
 
 pub fn boot_page_table() -> PageTable {

src/components/boot/loongarch64.rs

@@ -1,22 +1,22 @@
-use loongArch64::{
-    consts::{LOONGARCH_CSR_MAIL_BUF0, LOONGARCH_CSR_MAIL_BUF1},
-    iocsr::iocsr_read_d,
-    register::euen,
-};
+use loongArch64::register::euen;
 
 use crate::{
     arch::hart_id,
-    clear_bss,
     components::{
         common::CPU_NUM,
         consts::VIRT_ADDR_START,
-        debug_console::{display_info, println},
-        instruction::Instruction,
+        debug_console::{display_info, println, DebugConsole},
         percpu::percpu_area_init,
+        timer,
     },
+    instruction,
+    multicore::CpuCore,
     PageTable, PhysAddr,
 };
 
+#[cfg(feature = "trap")]
+use crate::components::trap;
+
 /// The earliest entry point for the primary CPU.
 ///
 /// We can't use bl to jump to higher address, so we use jirl to jump to higher address.
@@ -103,10 +103,14 @@ pub(crate) unsafe extern "C" fn _start_secondary() -> ! {
 ///
 /// This function will be called after assembly boot stage.
 pub fn rust_tmp_main(hart_id: usize) {
-    clear_bss();
-    percpu_area_init(hart_id);
+    super::clear_bss();
+    // Initialize CPU Configuration.
+    init_cpu();
+
+    CpuCore::init(hart_id);
+
     #[cfg(feature = "logger")]
-    crate::components::debug_console::DebugConsole::log_init();
+    DebugConsole::log_init();
 
     // Display Information.
     display_info!();
@@ -117,45 +121,39 @@ pub fn rust_tmp_main(hart_id: usize) {
     display_info!("Boot HART ID", "{}", hart_id);
     display_info!();
 
-    #[cfg(feature = "trap")]
-    crate::components::trap::set_trap_vector_base();
-    // Initialize CPU Configuration.
-    init_cpu();
-    crate::components::timer::init_timer();
-    #[cfg(feature = "trap")]
-    crate::components::trap::tlb_init(crate::components::trap::tlb_fill as _);
-
     // TODO: Detect CPU Num dynamically.
     CPU_NUM.init_by(2);
 
-    unsafe { crate::components::boot::_main_for_arch(hart_id) };
+    unsafe { super::_main_for_arch(hart_id) };
 
-    Instruction::shutdown();
+    instruction::shutdown();
 }
 
 /// Initialize CPU Configuration.
 fn init_cpu() {
     // Enable floating point
     euen::set_fpe(true);
-}
 
-/// The entry point for the second core.
-pub(crate) extern "C" fn _rust_secondary_main() {
-    let hart_id = hart_id();
-    percpu_area_init(hart_id);
+    // Initialize the percpu area for this hart.
+    percpu_area_init(hart_id());
 
-    log::info!("mailbox: {:#x}", iocsr_read_d(LOONGARCH_CSR_MAIL_BUF0));
-    log::info!("mailbox: {:#x}", iocsr_read_d(LOONGARCH_CSR_MAIL_BUF1));
+    // Initialzie Timer
+    timer::init_timer();
 
+    // Initialize the trap and tlb fill function
     #[cfg(feature = "trap")]
-    crate::components::trap::set_trap_vector_base();
+    {
+        trap::set_trap_vector_base();
+        trap::tlb_init(trap::tlb_fill as _);
+    }
+}
+
+/// The entry point for the second core.
+pub(crate) extern "C" fn _rust_secondary_main() {
     // Initialize CPU Configuration.
     init_cpu();
-    crate::components::timer::init_timer();
-    #[cfg(feature = "trap")]
-    crate::components::trap::tlb_init(crate::components::trap::tlb_fill as _);
 
-    unsafe { crate::components::boot::_main_for_arch(hart_id) };
+    unsafe { super::_main_for_arch(hart_id()) };
 }
 
 pub fn boot_page_table() -> PageTable {

src/components/boot/mod.rs

@@ -2,6 +2,8 @@
 //!
 //!
 
+use core::mem::size_of;
+
 // Define multi-architecture modules and pub use them.
 super::define_arch_mods!();
 
@@ -17,6 +19,21 @@ pub(crate) static mut BOOT_STACK: [u8; STACK_SIZE] = [0; STACK_SIZE];
 #[repr(align(4096))]
 pub(crate) struct PageAlignment([crate::pagetable::PTE; crate::PageTable::PTE_NUM_IN_PAGE]);
 
+/// Clear the bss section
+pub(crate) fn clear_bss() {
+    extern "C" {
+        fn _sbss();
+        fn _ebss();
+    }
+    unsafe {
+        core::slice::from_raw_parts_mut(
+            _sbss as usize as *mut u128,
+            (_ebss as usize - _sbss as usize) / size_of::<u128>(),
+        )
+        .fill(0);
+    }
+}
+
 // Declare the _main_for_arch exists.
 extern "Rust" {
     pub(crate) fn _main_for_arch(hartid: usize);

src/components/boot/riscv64.rs

@@ -4,8 +4,9 @@ use riscv::register::{sie, sstatus};
 use crate::components::common::{CPU_ID, CPU_NUM, DTB_PTR};
 use crate::components::consts::VIRT_ADDR_START;
 use crate::components::debug_console::{display_info, println};
-use crate::components::instruction::Instruction;
+use crate::components::instruction;
 use crate::components::pagetable::{PTEFlags, PTE};
+use crate::multicore::CpuCore;
 use crate::PageTable;
 
 use super::PageAlignment;
@@ -116,7 +117,7 @@ pub(crate) unsafe extern "C" fn secondary_start() -> ! {
 }
 
 pub(crate) fn rust_main(hartid: usize, device_tree: usize) {
-    crate::clear_bss();
+    super::clear_bss();
     #[cfg(feature = "logger")]
     crate::components::debug_console::DebugConsole::log_init();
     // Init allocator
@@ -125,6 +126,8 @@ pub(crate) fn rust_main(hartid: usize, device_tree: usize) {
     #[cfg(feature = "trap")]
     crate::components::trap::init();
 
+    CpuCore::init(hartid);
+
     // Initialize CPU Configuration.
     init_cpu();
 
@@ -154,7 +157,7 @@ pub(crate) fn rust_main(hartid: usize, device_tree: usize) {
     display_info!();
 
     unsafe { crate::components::boot::_main_for_arch(hartid) };
-    Instruction::shutdown();
+    instruction::shutdown();
 }
 
 /// Secondary Main function Entry.
@@ -176,7 +179,7 @@ pub(crate) extern "C" fn rust_secondary_main(hartid: usize) {
 
     log::info!("secondary hart {} started", hartid);
     unsafe { crate::components::boot::_main_for_arch(hartid) };
-    Instruction::shutdown();
+    instruction::shutdown();
 }
 
 #[inline]