From df6355f7a50b629e9e2361da1b3e7ab8f41790cf Mon Sep 17 00:00:00 2001
From: yufeng <321353225@qq.com>
Date: Wed, 7 Aug 2024 10:15:44 +0800
Subject: [PATCH] fix: fix some Code

---
 src/components/boot/riscv64.rs      | 4 ----
 src/components/pagetable/riscv64.rs | 4 ++--
 src/components/trap/mod.rs          | 2 +-
 src/components/trap/riscv64.rs      | 1 +
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/src/components/boot/riscv64.rs b/src/components/boot/riscv64.rs
index dd9a767..378d6b4 100644
--- a/src/components/boot/riscv64.rs
+++ b/src/components/boot/riscv64.rs
@@ -142,14 +142,10 @@ pub(crate) fn rust_main(hartid: usize, device_tree: usize) {
     crate::components::debug_console::DebugConsole::log_init();
     // Init allocator
     crate::components::percpu::set_local_thread_pointer(hartid);
-    println!("CPU_ID offset: {:#x}", CPU_ID.offset());
-    println!("init success, CPU_ID: {}", CPU_ID.read_current());
     CPU_ID.write_current(hartid);
     #[cfg(feature = "trap")]
     crate::components::trap::init();
 
-    println!("CPU_ID offset: {:#x}", CPU_ID.offset());
-
     unsafe {
         // Enable SUM for access user memory directly.
         // TODO: Call set_sum() for riscv version up than 1.0, Close when below 1.0
diff --git a/src/components/pagetable/riscv64.rs b/src/components/pagetable/riscv64.rs
index 0921f3f..8d7dbc2 100644
--- a/src/components/pagetable/riscv64.rs
+++ b/src/components/pagetable/riscv64.rs
@@ -184,7 +184,7 @@ impl PageTable {
     #[inline]
     pub fn restore(&self) {
         self.release();
-        let kernel_arr = Self::get_pte_list(crate::boot::boot_page_table().0);
+        let kernel_arr = Self::get_pte_list(Self::current().0);
         let arr = Self::get_pte_list(self.0);
         arr[0x100..].copy_from_slice(&kernel_arr[0x100..]);
         arr[0..0x100].fill(PTE(0));
@@ -193,7 +193,7 @@ impl PageTable {
     #[inline]
     pub fn change(&self) {
         // Write page table entry for
-        satp::write((8 << 60) | (self.0 .0 >> 12));
+        satp::write((8 << 60) | (self.0.0 >> 12));
         TLB::flush_all();
     }
 }
diff --git a/src/components/trap/mod.rs b/src/components/trap/mod.rs
index c788c4a..8144684 100644
--- a/src/components/trap/mod.rs
+++ b/src/components/trap/mod.rs
@@ -21,7 +21,7 @@ pub enum TrapType {
     Irq(IRQVector),
 }
 
-#[derive(Debug, Clone, Copy)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub enum EscapeReason {
     NoReason,
     IRQ,
diff --git a/src/components/trap/riscv64.rs b/src/components/trap/riscv64.rs
index 6e95c68..3d0fa3b 100644
--- a/src/components/trap/riscv64.rs
+++ b/src/components/trap/riscv64.rs
@@ -121,6 +121,7 @@ fn kernel_callback(context: &mut TrapFrame) -> TrapType {
             TrapType::Timer
         }
         Trap::Exception(Exception::StorePageFault) => TrapType::StorePageFault(stval),
+        Trap::Exception(Exception::StoreFault) => TrapType::StorePageFault(stval),
         Trap::Exception(Exception::InstructionPageFault) => TrapType::InstructionPageFault(stval),
         Trap::Exception(Exception::IllegalInstruction) => TrapType::IllegalInstruction(stval),
         Trap::Exception(Exception::LoadPageFault) => TrapType::LoadPageFault(stval),