fmt: Format code and fix some clippy

src/addr.rs

@@ -215,7 +215,7 @@ impl PhysPage {
 
     #[inline]
     pub fn copy_value_from_another(&self, ppn: PhysPage) {
-        self.get_buffer().copy_from_slice(&ppn.get_buffer());
+        self.get_buffer().copy_from_slice(ppn.get_buffer());
         #[cfg(c906)]
         unsafe {
             asm!(".long 0x0010000b"); // dcache.all

src/components/arch/aarch64.rs

@@ -26,10 +26,10 @@ pub(crate) fn arch_init() {
     }
     DTB_BIN.init_by(buffer);
     if let Ok(fdt) = Fdt::new(&DTB_BIN) {
-        info!("There has {} CPU(s)", fdt.cpus().count());
+        log::info!("There has {} CPU(s)", fdt.cpus().count());
         let mut mem_area = Vec::new();
         fdt.memory().regions().for_each(|x| {
-            info!(
+            log::info!(
                 "memory region {:#X} - {:#X}",
                 x.starting_address as usize,
                 x.starting_address as usize + x.size.unwrap()

src/components/arch/aarch64/psci.rs

@@ -94,9 +94,9 @@ fn psci_call(func: u32, arg0: usize, arg1: usize, arg2: usize) -> Result<(), Psc
 
 /// Shutdown the whole system, including all CPUs.
 pub fn system_off() -> ! {
-    info!("Shutting down...");
+    log::info!("Shutting down...");
     psci_call(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0).ok();
-    warn!("It should shutdown!");
+    log::warn!("It should shutdown!");
     loop {
         // crate::arch::halt();
     }
@@ -111,10 +111,10 @@ pub fn system_off() -> ! {
 /// `entry_point` is the physical address of the secondary CPU's entry point.
 /// `arg` will be passed to the `X0` register of the secondary CPU.
 pub fn cpu_on(target_cpu: usize, entry_point: usize, arg: usize) {
-    info!("Starting CPU {:x} ON ...", target_cpu);
+    log::info!("Starting CPU {:x} ON ...", target_cpu);
     let res = psci_call(PSCI_0_2_FN64_CPU_ON, target_cpu, entry_point, arg);
     if let Err(e) = res {
-        error!("failed to boot CPU {:x} ({:?})", target_cpu, e);
+        log::error!("failed to boot CPU {:x} ({:?})", target_cpu, e);
     }
 }
 

src/components/arch/loongarch64.rs

@@ -1,18 +1,17 @@
+use alloc::vec;
 use alloc::vec::Vec;
 
 use crate::components::{common::{DTB_BIN, MEM_AREA}, consts::VIRT_ADDR_START};
 
 
 pub(crate) fn arch_init() {
     DTB_BIN.init_by(Vec::new());
-    MEM_AREA.init_by({
-        let mut mem_area = Vec::new();
-        // This is just temporary solution until we find a better way to detect memory areas.
-        mem_area.push((VIRT_ADDR_START | 0x9000_0000, 0x2000_0000));
-        mem_area
-    });
+    MEM_AREA.init_by(vec![
+        (VIRT_ADDR_START | 0x9000_0000, 0x2000_0000)
+    ]);
 }
 
+#[inline]
 pub fn hart_id() -> usize {
     loongArch64::register::cpuid::read().core_id()
 }

src/components/arch/riscv64.rs

@@ -32,9 +32,9 @@ pub fn arch_init() {
     DTB_BIN.init_by(buffer);
     let mut mem_area = Vec::new();
     if let Ok(fdt) = Fdt::new(&DTB_BIN) {
-        info!("There has {} CPU(s)", fdt.cpus().count());
+        log::info!("There has {} CPU(s)", fdt.cpus().count());
         fdt.memory().regions().for_each(|x| {
-            info!(
+            log::info!(
                 "memory region {:#X} - {:#X}",
                 x.starting_address as usize,
                 x.starting_address as usize + x.size.unwrap()

src/components/boot/loongarch64.rs

@@ -1,6 +1,11 @@
-use loongArch64::register::euen;
+use loongArch64::{
+    consts::{LOONGARCH_CSR_MAIL_BUF0, LOONGARCH_CSR_MAIL_BUF1},
+    iocsr::iocsr_read_d,
+    register::euen,
+};
 
 use crate::{
+    arch::hart_id,
     clear_bss,
     components::{
         common::CPU_NUM,
@@ -27,6 +32,10 @@ unsafe extern "C" fn _start() -> ! {
         lu52i.d     $t0, $t0, -1792     # CA, PLV0, 0x9000 xxxx xxxx xxxx
         csrwr       $t0, 0x181          # LOONGARCH_CSR_DMWIN1
 
+        # Goto 1 if hart is not 0
+        csrrd       $t1, 0x20       # read cpu from csr
+        bnez        $t1, 1f
+
         # Enable PG 
         li.w		$t0, 0xb0		# PLV=0, IE=0, PG=1
         csrwr		$t0, 0x0        # LOONGARCH_CSR_CRMD
@@ -42,10 +51,19 @@ unsafe extern "C" fn _start() -> ! {
         csrrd       $a0, 0x20           # cpuid
         la.global   $t0, {entry}
         jirl        $zero,$t0,0
+
+    1:
+        li.w        $s0, {MBUF0}
+        iocsrrd.d   $t0, $s0
+        la.global   $t1, {sec_entry}
+        bne         $t0, $t1, 1b
+        jirl        $zero, $t1, 0
         ",
         boot_stack_size = const crate::components::boot::STACK_SIZE,
         boot_stack = sym crate::components::boot::BOOT_STACK,
+        MBUF0 = const loongArch64::consts::LOONGARCH_CSR_MAIL_BUF0,
         entry = sym rust_tmp_main,
+        sec_entry = sym _start_secondary,
         options(noreturn),
     )
 }
@@ -67,18 +85,16 @@ pub(crate) unsafe extern "C" fn _start_secondary() -> ! {
         lu52i.d      $t0, $t0, -1792     # CA, PLV0, 0x9000 xxxx xxxx xxxx
         csrwr        $t0, 0x181          # LOONGARCH_CSR_DMWIN1
 
-        la.abs       $sp, {sec_boot_stack_top}
-        li.d         $t0, {boot_stack_size}
-        add.d        $sp, $sp, $t0       # setup boot stack
+        li.w         $t0, {MBUF1}
+        iocsrrd.d    $sp, $t0
 
-        csrrd $a0, 0x20                  # cpuid
-        la.global $t0, {entry}
+        csrrd        $a0, 0x20                  # cpuid
+        la.global    $t0, {entry}
 
         jirl $zero,$t0,0
         ",
         options(noreturn),
-        sec_boot_stack_top = sym crate::components::boot::BOOT_STACK,
-        boot_stack_size = const crate::components::boot::STACK_SIZE,
+        MBUF1 = const loongArch64::consts::LOONGARCH_CSR_MAIL_BUF1,
         entry = sym _rust_secondary_main,
     )
 }
@@ -124,17 +140,21 @@ fn init_cpu() {
 }
 
 /// The entry point for the second core.
-pub(crate) extern "C" fn _rust_secondary_main(hart_id: usize) {
+pub(crate) extern "C" fn _rust_secondary_main() {
+    let hart_id = hart_id();
     percpu_area_init(hart_id);
 
+    log::info!("mailbox: {:#x}", iocsr_read_d(LOONGARCH_CSR_MAIL_BUF0));
+    log::info!("mailbox: {:#x}", iocsr_read_d(LOONGARCH_CSR_MAIL_BUF1));
+
     #[cfg(feature = "trap")]
     crate::components::trap::set_trap_vector_base();
     // Initialize CPU Configuration.
     init_cpu();
     crate::components::timer::init_timer();
     #[cfg(feature = "trap")]
     crate::components::trap::tlb_init(crate::components::trap::tlb_fill as _);
-    
+
     unsafe { crate::components::boot::_main_for_arch(hart_id) };
 }
 

src/components/boot/riscv64.rs

@@ -174,7 +174,7 @@ pub(crate) extern "C" fn rust_secondary_main(hartid: usize) {
     // Initialize CPU Configuration.
     init_cpu();
 
-    info!("secondary hart {} started", hartid);
+    log::info!("secondary hart {} started", hartid);
     unsafe { crate::components::boot::_main_for_arch(hartid) };
     Instruction::shutdown();
 }

src/components/consts/mod.rs

@@ -11,6 +11,6 @@ pub const VIRT_ADDR_START: usize = GenericConfig::VIRT_ADDR;
 struct GenericConfig;
 
 /// Configuration Trait, Bound for configs
-pub(self) trait ConfigTrait {
+trait ConfigTrait {
     const VIRT_ADDR: usize;
 }

src/components/debug_console/mod.rs

@@ -50,7 +50,7 @@ pub struct DebugConsole;
 // Write string through DebugConsole
 impl Write for DebugConsole {
     fn write_str(&mut self, s: &str) -> core::fmt::Result {
-        s.as_bytes().into_iter().for_each(|x| Self::putchar(*x));
+        s.as_bytes().iter().for_each(|x| Self::putchar(*x));
         Ok(())
     }
 }

src/components/irq/aarch64.rs

@@ -28,7 +28,7 @@ static GICC: GicCpuInterface = GicCpuInterface::new(GICC_BASE.get_mut_ptr());
 
 /// Initializes GICD, GICC on the primary CPU.
 pub(crate) fn init() {
-    info!("Initialize GICv2...");
+    log::info!("Initialize GICv2...");
     GICD.lock().init();
     GICC.init();
 }

src/components/macros.rs

@@ -0,0 +1,39 @@
+#[cfg(target_arch = "loongarch64")]
+#[macro_export]
+macro_rules! pub_use_arch {
+    ($($name:ident),*) => {
+        $(
+            pub use self::loongarch64::$name;
+        )*
+    };
+}
+
+#[cfg(target_arch = "x86_64")]
+#[macro_export]
+macro_rules! pub_use_arch {
+    ($($name:ident),*) => {
+        $(
+            pub use self::x86_64::$name;
+        )*
+    };
+}
+
+#[cfg(target_arch = "riscv64")]
+#[macro_export]
+macro_rules! pub_use_arch {
+    ($($name:ident),*) => {
+        $(
+            pub use self::riscv64::$name;
+        )*
+    };
+}
+
+#[cfg(target_arch = "aarch64")]
+#[macro_export]
+macro_rules! pub_use_arch {
+    ($($name:ident),*) => {
+        $(
+            pub use self::aarch64::$name;
+        )*
+    };
+}

src/components/mod.rs

@@ -10,6 +10,7 @@ pub mod debug_console;
 pub mod instruction;
 pub mod irq;
 pub mod kcontext;
+pub mod macros;
 pub mod mem;
 #[cfg(feature = "multicore")]
 pub mod multicore;
@@ -20,4 +21,4 @@ pub mod timer;
 pub mod trap;
 pub mod trapframe;
 
-pub(self) use polyhal_macro::define_arch_mods;
+use polyhal_macro::define_arch_mods;

src/components/multicore/aarch64.rs

@@ -1,5 +1,10 @@
 use crate::components::multicore::MultiCore;
 
+// TODO: Boot a core with top pointer of the stack
+pub fn boot_core(_hart_id: usize, _sp_top: usize) {
+    log::error!("Boot Core is not implemented yet for aarch64");
+}
+
 impl MultiCore {
     /// Boot application cores
     pub fn boot_all() {}

src/components/multicore/loongarch64.rs

@@ -1,11 +1,20 @@
 use loongArch64::ipi::{csr_mail_send, send_ipi_single};
 
-use crate::components::multicore::MultiCore;
+use crate::{boot::BOOT_STACK, components::multicore::MultiCore};
+
+// TODO: Boot a core with top pointer of the stack
+pub fn boot_core(hart_id: usize, sp_top: usize) {
+    csr_mail_send(crate::components::boot::_start_secondary as _, hart_id, 0);
+    csr_mail_send(sp_top as _, hart_id, 1);
+    send_ipi_single(1, 1);
+}
 
 impl MultiCore {
     pub fn boot_all() {
+        // Stack Pointer.
+        let stack_ptr = unsafe { BOOT_STACK.as_ptr() as u64 + BOOT_STACK.len() as u64 };
         csr_mail_send(crate::components::boot::_start_secondary as _, 1, 0);
+        csr_mail_send(stack_ptr, 1, 1);
         send_ipi_single(1, 1);
-        loop {}
     }
 }

src/components/multicore/mod.rs

@@ -15,6 +15,19 @@
 //! Here will have more functionality about multicore in the future.
 //!
 
+use crate::{pub_use_arch, utils::MutexNoIrq};
+
 pub struct MultiCore;
 
+static CORE_SET: MutexNoIrq<u64> = MutexNoIrq::new(0);
+
+pub struct CpuCore;
+
+/// Initialize the core with boot_hart_id
+pub(crate) fn init(boot_hart_id: usize) {
+    let mut set = CORE_SET.lock();
+    *set |= 1 << boot_hart_id;
+}
+
 super::define_arch_mods!();
+pub_use_arch!(boot_core);

src/components/multicore/riscv64.rs

@@ -1,12 +1,29 @@
 use crate::{
-    components::{
-        common::{frame_alloc, CPU_ID, CPU_NUM},
-        consts::{MULTI_CORE_AREA, MULTI_CORE_AREA_SIZE, VIRT_ADDR_START},
-        multicore::MultiCore,
-    },
+    boot::secondary_start,
+    common::{frame_alloc, CPU_ID, CPU_NUM},
+    consts::{MULTI_CORE_AREA, MULTI_CORE_AREA_SIZE, VIRT_ADDR_START},
+    multicore::MultiCore,
     MappingFlags, MappingSize, PageTable,
 };
 
+// TODO: Boot a core with top pointer of the stack
+pub fn boot_core(cpu: usize, sp_top: usize) {
+    if cpu == CPU_ID.read_current() {
+        return;
+    };
+
+    // PERCPU DATA ADDRESS RANGE END
+    let aux_core_func = (secondary_start as usize) & (!VIRT_ADDR_START);
+
+    log::info!("secondary addr: {:#x}", secondary_start as usize);
+    let ret = sbi_rt::hart_start(cpu, aux_core_func, sp_top);
+    if ret.is_ok() {
+        log::info!("hart {} Startting successfully", cpu);
+    } else {
+        log::warn!("hart {} Startting failed", cpu)
+    }
+}
+
 /// Implement the function for multicore
 impl MultiCore {
     /// Boot all application cores.
@@ -36,12 +53,12 @@ impl MultiCore {
                 )
             }
 
-            info!("secondary addr: {:#x}", secondary_start as usize);
+            log::info!("secondary addr: {:#x}", secondary_start as usize);
             let ret = sbi_rt::hart_start(cpu, aux_core_func, cpu_addr_end);
             if ret.is_ok() {
-                info!("hart {} Startting successfully", cpu);
+                log::info!("hart {} Startting successfully", cpu);
             } else {
-                warn!("hart {} Startting failed", cpu)
+                log::warn!("hart {} Startting failed", cpu)
             }
         });
     }

src/components/multicore/x86_64.rs

@@ -1,5 +1,10 @@
 use crate::components::multicore::MultiCore;
 
+// TODO: Boot a core with top pointer of the stack
+pub fn boot_core(_hart_id: usize, _sp_top: usize) {
+    log::error!("Boot Core is not implemented yet for aarch64");
+}
+
 impl MultiCore {
     pub fn boot_all() {}
 }