feat: publish polyhal

Cargo.toml

@@ -11,15 +11,15 @@ repository = "https://github.com/Byte-OS/polyhal"
 
 [features]
 kcontext = []
-multicore = []
-interrupt = []
+multicore = ["boot"]
+trap = []
 boot = []
 logger = []
 
 vga_text = []
 graphic = []
 
-default = ["multicore", "interrupt", "boot", "kcontext"]
+default = ["boot", "trap", "kcontext"]
 
 [dependencies]
 log = "0.4"

src/components/boot/mod.rs

@@ -15,6 +15,5 @@ pub(crate) static mut BOOT_STACK: [u8; STACK_SIZE] = [0; STACK_SIZE];
 
 // Declare the _main_for_arch exists.
 extern "Rust" {
-    #[cfg(feature = "boot")]
     pub(crate) fn _main_for_arch(hartid: usize);
 }

src/components/pagetable/riscv64.rs

@@ -4,7 +4,6 @@ use bitflags::bitflags;
 use riscv::register::satp;
 
 use crate::addr::{PhysAddr, PhysPage, VirtAddr, VirtPage};
-use crate::components::boot::boot_page_table;
 
 use crate::components::pagetable::{MappingFlags, PageTable, PTE, TLB};
 use crate::utils::bit;
@@ -185,7 +184,7 @@ impl PageTable {
     #[inline]
     pub fn restore(&self) {
         self.release();
-        let kernel_arr = Self::get_pte_list(boot_page_table().0);
+        let kernel_arr = Self::get_pte_list(crate::boot::boot_page_table().0);
         let arr = Self::get_pte_list(self.0);
         arr[0x100..].copy_from_slice(&kernel_arr[0x100..]);
         arr[0..0x100].fill(PTE(0));