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feat: new new percpu design for all arch
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,69 +1,27 @@ | ||
use std::mem::size_of; | ||
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use quote::quote; | ||
use syn::{Ident, Type}; | ||
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pub fn gen_offset(symbol: &Ident) -> proc_macro2::TokenStream { | ||
quote! { | ||
let value: usize; | ||
unsafe { | ||
cfg_match! { | ||
cfg(target_arch = "x86_64") => { | ||
::core::arch::asm!( | ||
"movabs {0}, offset {VAR}", | ||
out(reg) value, | ||
VAR = sym #symbol, | ||
); | ||
} | ||
cfg(target_arch = "aarch64") => { | ||
::core::arch::asm!( | ||
"movz {0}, #:abs_g0_nc:{VAR}", | ||
out(reg) value, | ||
VAR = sym #symbol, | ||
); | ||
} | ||
cfg(any(target_arch = "riscv32", target_arch = "riscv64")) => { | ||
::core::arch::asm!( | ||
"lui {0}, %hi({VAR})", | ||
"addi {0}, {0}, %lo({VAR})", | ||
out(reg) value, | ||
VAR = sym #symbol, | ||
); | ||
} | ||
cfg(target_arch = "loongarch64") => { | ||
::core::arch::asm!( | ||
"la.abs {0}, {VAR}", | ||
out(reg) value, | ||
VAR = sym #symbol, | ||
); | ||
} | ||
} | ||
} | ||
value | ||
} | ||
} | ||
/// Reserved for default usage, Just for x86_64 now. | ||
pub const PERCPU_RESERVED: usize = 4 * size_of::<usize>(); | ||
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pub fn gen_current_ptr(symbol: &Ident, ty: &Type) -> proc_macro2::TokenStream { | ||
pub fn gen_current_ptr(_symbol: &Ident, ty: &Type) -> proc_macro2::TokenStream { | ||
// TODO: Move this consts into polyhal crate. | ||
quote! { | ||
let base: usize; | ||
// The first index is SELF_PTR in the x86_64 format | ||
#[cfg(target_arch = "x86_64")] | ||
{ | ||
// `__PERCPU_SELF_PTR` stores GS_BASE, which is defined in crate `percpu`. | ||
::core::arch::asm!( | ||
"mov {0}, gs:[offset __PERCPU_SELF_PTR]", | ||
"add {0}, offset {VAR}", | ||
out(reg) base, | ||
VAR = sym #symbol, | ||
); | ||
base as *const #ty | ||
} | ||
#[cfg(not(target_arch = "x86_64"))] | ||
{ | ||
#[cfg(target_arch = "aarch64")] | ||
::core::arch::asm!("mrs {}, TPIDR_EL1", out(reg) base); | ||
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] | ||
::core::arch::asm!("mv {}, gp", out(reg) base); | ||
#[cfg(target_arch = "loongarch64")] | ||
::core::arch::asm!("move {}, $r21", out(reg) base); | ||
(base + self.offset()) as *const #ty | ||
} | ||
::core::arch::asm!( | ||
"mov {0}, gs:0", | ||
out(reg) base, | ||
); | ||
#[cfg(target_arch = "aarch64")] | ||
::core::arch::asm!("mrs {}, TPIDR_EL1", out(reg) base); | ||
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] | ||
::core::arch::asm!("mv {}, gp", out(reg) base); | ||
#[cfg(target_arch = "loongarch64")] | ||
::core::arch::asm!("move {}, $r21", out(reg) base); | ||
(base + self.offset()) as *const #ty | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,5 +1,12 @@ | ||
use core::mem::size_of; | ||
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pub const VIRT_ADDR_START: usize = 0xffff_ff80_0000_0000; | ||
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pub const SYSCALL_VECTOR: usize = 0x33445566; | ||
/// The offset of the pic irq. | ||
pub(super) const PIC_VECTOR_OFFSET: u8 = 0x20; | ||
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/// Reserved percpu index | ||
pub(super) const PERCPU_USER_RSP_OFFSET: usize = 1 * size_of::<usize>(); | ||
pub(super) const PERCPU_KERNEL_RSP_OFFSET: usize = 2 * size_of::<usize>(); | ||
pub(super) const PERCPU_USER_CONTEXT_OFFSET: usize = 3 * size_of::<usize>(); |
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