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app-versions-9-0.tex
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app-versions-9-0.tex
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This version of the \textit{CHERI Instruction-Set Architecture} is a full
release of the Version 9 specification:
\begin{itemize}
\item We have shifted to CHERI-RISC-V as our primary reference
platform instead of CHERI-MIPS. This included several changes to
Chapter~\ref{chap:model} and Chapter~\ref{chap:architecture} to
replace MIPS-specific details with more architectural-neutral
concepts.
Section~\ref{section:protection-domain-transition-with-cinvoke} was
also moved to Chapter~\ref{chap:architecture}.
\item The privileged architecture portions of CHERI-RISC-V are now
defined as an extension to version 1.11 of the RISC-V privileged
architecture specification.
\item CHERI-RISC-V reports capability exception details in \xtval{}
rather than \xccsr{}.
\item The RISC-V \insnnoref{JAL} and \insnnoref{JALR} instructions are
now mode-dependent meaning that they use capability register
operands in capability mode rather than always using integer
registers. The capability mode version of these instructions are
named \insnref{CJAL} and \insnref{CJALR}. The previous
\insnnoref{CJALR} instruction has been renamed to
\insnref{JALR.CAP}. In addition, \insnref{JALR.PCC} has been added
to permit integer jump and links in capability mode.
\item Section~\ref{subsection:compressed-instructions} has been
rewritten to reflect an initial implementation of CHERI-RISC-V
compressed instructions in capability encoding mode.
\item Opcode encodings have been reserved for CHERI-RISC-V memory
versioning instructions as well as \insnnoref{CRelocate}.
\item CHERI-RISC-V always uses a merged register file and the
architecture-neutral chapters now assume a merged register file on
all CHERI architectures. This included removing the dirty bit from
\xccsr{} as well as the \insnnoref{CGetAddr}, \insnnoref{Clear}, and
\insnnoref{CSub} instructions.
\item CHERI-RISC-V clears tags rather than raising exceptions for
non-monotonic modifications to capabilities.
\item Added \insnref{CGetHigh} and \insnref{CSetHigh} to retrieve and
modify the upper half of a capability.
\item Added \insnref{CGetTop} to retrieve the upper limit of a
capability.
\item \DDC{} and \PCC{} no longer relocate legacy memory accesses.
These registers still constrain legacy memory accesses. This
included deprecating \insnref{CFromPtr} and \insnref{CToPtr}.
\item Removed CHERI-MIPS from the specification as it is deprecated
and no longer actively developed.
\item Added a new section in Chapter~\ref{chap:model} describing
potential uses of capabilities to protect physical addresses.
\item CHERI-RISC-V now enables/disables CHERI extensions via a bit in
the \menvcfg{} and \senvcfg{} CSRs rather than \xccsr{}.
\item CHERI-RISC-V \xScratchC{} capability registers now extend the
existing \xscratch{} registers.
\item We have expanded the CHERI-x86-64 sketch in
Chapter~\ref{chap:cheri-x86-64} to include details on extensions to
existing instructions to support operations on capabilities as well
as details for new instructions in a new ISA reference in
Chapter~\ref{chap:isaref-x86-64}.
\item Added a description of the 64-bit CHERI Concentrate capability
format.
\end{itemize}