[CHERI-RISC-V] Allow load/store mnemonics without the c prefix [4/n]

This adds support for compressed instructions. Does not yet include Zcb or floating-point loads/stores.
CTSRD-CHERI · Sep 4, 2024 · 053ca71 · 053ca71
1 parent 9bc635d
commit 053ca71
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Showing 5 changed files with 72 additions and 2 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
@@ -1135,7 +1135,21 @@ def : InstAlias<"c.cincoffsetimm4cspn $rd, $rs1, $imm",
                 (C_CIncOffsetImm4CSPN GPCRC:$rd, CSP:$rs1, uimm10_lsb00nonzero:$imm), 0>;
 def : InstAlias<"c.cincoffsetimm16csp $rd, $imm",
                 (C_CIncOffsetImm16CSP CSP:$rd, simm10_lsb0000nonzero:$imm), 0>;
+def : MnemonicAlias<"c.lw", "c.clw">;
+def : MnemonicAlias<"c.sw", "c.csw">;
+def : MnemonicAlias<"c.sc", "c.csc">;
+def : MnemonicAlias<"c.lc", "c.clc">;
+def : MnemonicAlias<"c.lwsp", "c.clwcsp">;
+def : MnemonicAlias<"c.swsp", "c.cswcsp">;
+def : MnemonicAlias<"c.scsp", "c.csccsp">;
+def : MnemonicAlias<"c.lcsp", "c.clccsp">;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
+let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
+def : MnemonicAlias<"c.ld", "c.cld">;
+def : MnemonicAlias<"c.sd", "c.csd">;
+def : MnemonicAlias<"c.ldsp", "c.cldcsp">;
+def : MnemonicAlias<"c.sdsp", "c.csdcsp">;
+} // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns

diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s
@@ -29,6 +29,14 @@ c.csw a5, 1(ca3)
 # TODO-RV64-NO-C: <stdin>:[[#@LINE-5]]:11: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
 # CHECK-RV64-NO-C: <stdin>:[[#@LINE-6]]:11: error: invalid operand for instruction
 
+c.csw a5, 4(a3)
+# CHECK: <stdin>:[[#@LINE-1]]:13: error: invalid operand for instruction
+c.sw a5, 4(a3)
+# CHECK-RV32-NO-C: <stdin>:[[#@LINE-1]]:1: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), Not Capability Mode
+# CHECK-RV32-C: <stdin>:[[#@LINE-2]]:12: error: invalid operand for instruction
+# CHECK-RV64-NO-C: <stdin>:[[#@LINE-3]]:1: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), Not Capability Mode
+# CHECK-RV64-C: <stdin>:[[#@LINE-4]]:12: error: invalid operand for instruction
+
 # Bad operands:
 c.cjalr a1
 # CHECK: <stdin>:[[#@LINE-1]]:9: error: invalid operand for instruction

diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s
@@ -9,18 +9,30 @@
 # CHECK-ASM-AND-OBJ: c.clccsp cra, 40(csp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x70]
 c.clccsp cra, 40(csp)
+# CHECK-ASM-AND-OBJ: c.clccsp cra, 40(csp)
+# CHECK-ASM-SAME: encoding: [0xa2,0x70]
+c.lcsp cra, 40(csp)
 # CHECK-ASM-AND-OBJ: c.csccsp cra, 256(csp)
 # CHECK-ASM-SAME: encoding: [0x06,0xe2]
 c.csccsp cra, 256(csp)
+# CHECK-ASM-AND-OBJ: c.csccsp cra, 256(csp)
+# CHECK-ASM-SAME: encoding: [0x06,0xe2]
+c.scsp cra, 256(csp)
 # CHECK-ASM-AND-OBJ: c.clc ca2, 16(ca0)
 # CHECK-ASM-SAME: encoding: [0x10,0x69]
 c.clc ca2, 16(ca0)
+# CHECK-ASM-AND-OBJ: c.clc ca2, 16(ca0)
+# CHECK-ASM-SAME: encoding: [0x10,0x69]
+c.lc ca2, 16(ca0)
 # CHECK-ASM-AND-OBJ: c.csc ca5, 128(ca3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xe2]
 c.csc ca5, 128(ca3)
+# CHECK-ASM-AND-OBJ: c.csc ca5, 128(ca3)
+# CHECK-ASM-SAME: encoding: [0xdc,0xe2]
+c.sc ca5, 128(ca3)
 
 ## C.JAL is only defined for RV32C:
-# CHECK-OBJ: c.cjal 0x806
+# CHECK-OBJ: c.cjal 0x80e
 # CHECK-ASM: c.cjal 2046
 # CHECK-ASM-SAME: encoding: [0xfd,0x2f]
 c.cjal 2046
diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s
@@ -12,15 +12,27 @@
 # CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(csp)
 # CHECK-ASM-SAME: encoding: [0x82,0x40]
 c.clwcsp ra, 0(csp)
+# CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(csp)
+# CHECK-ASM-SAME: encoding: [0x82,0x40]
+c.lwsp ra, 0(csp)
 # CHECK-ASM-AND-OBJ: c.cswcsp ra, 252(csp)
 # CHECK-ASM-SAME: encoding: [0x86,0xdf]
 c.cswcsp ra, 252(csp)
+# CHECK-ASM-AND-OBJ: c.cswcsp ra, 252(csp)
+# CHECK-ASM-SAME: encoding: [0x86,0xdf]
+c.swsp ra, 252(csp)
 # CHECK-ASM-AND-OBJ: c.clw a2, 0(ca0)
 # CHECK-ASM-SAME: encoding: [0x10,0x41]
 c.clw a2, 0(ca0)
+# CHECK-ASM-AND-OBJ: c.clw a2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x10,0x41]
+c.lw a2, 0(ca0)
 # CHECK-ASM-AND-OBJ: c.csw a5, 124(ca3)
 # CHECK-ASM-SAME: encoding: [0xfc,0xde]
 c.csw a5, 124(ca3)
+# CHECK-ASM-AND-OBJ: c.csw a5, 124(ca3)
+# CHECK-ASM-SAME: encoding: [0xfc,0xde]
+c.sw a5, 124(ca3)
 
 # CHECK-ASM-AND-OBJ: c.cjr ca7
 # CHECK-ASM-SAME: encoding: [0x82,0x88]

diff --git a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s
@@ -8,25 +8,49 @@
 # CHECK-ASM-AND-OBJ: c.clccsp cra, 32(csp)
 # CHECK-ASM-SAME: encoding: [0x82,0x30]
 c.clccsp cra, 32(csp)
+# CHECK-ASM-AND-OBJ: c.clccsp cra, 32(csp)
+# CHECK-ASM-SAME: encoding: [0x82,0x30]
+c.lcsp cra, 32(csp)
 # CHECK-ASM-AND-OBJ-NEXT: c.csccsp cra, 256(csp)
 # CHECK-ASM-SAME: encoding: [0x06,0xa2]
 c.csccsp cra, 256(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.csccsp cra, 256(csp)
+# CHECK-ASM-SAME: encoding: [0x06,0xa2]
+c.scsp cra, 256(csp)
 # CHECK-ASM-AND-OBJ-NEXT: c.clc ca2, 16(ca0)
 # CHECK-ASM-SAME: encoding: [0x10,0x29]
 c.clc ca2, 16(ca0)
+# CHECK-ASM-AND-OBJ-NEXT: c.clc ca2, 16(ca0)
+# CHECK-ASM-SAME: encoding: [0x10,0x29]
+c.lc ca2, 16(ca0)
 # CHECK-ASM-AND-OBJ-NEXT: c.csc ca5, 128(ca3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xa2]
 c.csc ca5, 128(ca3)
+# CHECK-ASM-AND-OBJ-NEXT: c.csc ca5, 128(ca3)
+# CHECK-ASM-SAME: encoding: [0xdc,0xa2]
+c.sc ca5, 128(ca3)
 ## *D operations need RV64C:
 # CHECK-ASM-AND-OBJ-NEXT: c.cldcsp ra, 40(csp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x70]
 c.cldcsp ra, 40(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.cldcsp ra, 40(csp)
+# CHECK-ASM-SAME: encoding: [0xa2,0x70]
+c.ldsp ra, 40(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.csdcsp ra, 256(csp)
+# CHECK-ASM-SAME: encoding: [0x06,0xe2]
+c.sdsp ra, 256(csp)
 # CHECK-ASM-AND-OBJ-NEXT: c.csdcsp ra, 256(csp)
 # CHECK-ASM-SAME: encoding: [0x06,0xe2]
-c.csdcsp ra, 256(csp)
+c.sdsp ra, 256(csp)
 # CHECK-ASM-AND-OBJ-NEXT: c.cld a2, 16(ca0)
 # CHECK-ASM-SAME: encoding: [0x10,0x69]
 c.cld a2, 16(ca0)
+# CHECK-ASM-AND-OBJ-NEXT: c.cld a2, 16(ca0)
+# CHECK-ASM-SAME: encoding: [0x10,0x69]
+c.ld a2, 16(ca0)
 # CHECK-ASM-AND-OBJ-NEXT: c.csd a5, 128(ca3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xe2]
 c.csd a5, 128(ca3)
+# CHECK-ASM-AND-OBJ-NEXT: c.csd a5, 128(ca3)
+# CHECK-ASM-SAME: encoding: [0xdc,0xe2]
+c.sd a5, 128(ca3)