From 35604c06494b8646af466c154e0144cd8c52ce5d Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 26 Aug 2024 23:45:39 -0700 Subject: [PATCH] [CHERI-RISC-V] Allow load/store mnemonics without the c prefix [5/n] This adds the floating point loads and stores and should conclude this series of patches. --- llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td | 25 ++++++++++++++++--- .../cheri/rv32fdcxcheri-cap-mode-only-valid.s | 12 +++++++++ .../RISCV/cheri/rv32fdxcheri-cap-mode-valid.s | 25 ++++++++++++++++++- 3 files changed, 57 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td index 378bf228d2d0..535a2c658978 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td @@ -916,8 +916,13 @@ def CFSW : RVInstS<0b010, OPC_STORE_FP, (outs), (ins FPR32:$rs2, GPCR:$rs1, simm12:$imm12), "cfsw", "$rs2, ${imm12}(${rs1})">; -def : InstAlias<"cflw $rd, (${rs1})", (CFLW FPR32:$rd, GPCR:$rs1, 0), 0>; -def : InstAlias<"cfsw $rs2, (${rs1})", (CFSW FPR32:$rs2, GPCR:$rs1, 0), 0>; +defm : CPrefixedInstAlias<"flw $rd, (${rs1})", (CFLW FPR32:$rd, GPCR:$rs1, 0)>; +defm : CPrefixedInstAlias<"fsw $rs2, (${rs1})", + (CFSW FPR32:$rs2, GPCR:$rs1, 0)>; +def : InstAlias<"flw $rd, ${imm12}(${rs1})", + (CFLW FPR32:$rd, GPCR:$rs1, simm12:$imm12), 0>; +def : InstAlias<"fsw $rs2, ${imm12}(${rs1})", + (CFSW FPR32:$rs2, GPCR:$rs1, simm12:$imm12), 0>; } // Predicates = [HasCheri, HasStdExtF, IsCapMode] /// 'D' (Single-Precision Floating-Point) extension @@ -935,8 +940,13 @@ def CFSD : RVInstS<0b011, OPC_STORE_FP, (outs), (ins FPR64:$rs2, GPCR:$rs1, simm12:$imm12), "cfsd", "$rs2, ${imm12}(${rs1})">; -def : InstAlias<"cfld $rd, (${rs1})", (CFLD FPR64:$rd, GPCR:$rs1, 0), 0>; -def : InstAlias<"cfsd $rs2, (${rs1})", (CFSD FPR64:$rs2, GPCR:$rs1, 0), 0>; +defm : CPrefixedInstAlias<"fld $rd, (${rs1})", (CFLD FPR64:$rd, GPCR:$rs1, 0)>; +defm : CPrefixedInstAlias<"fsd $rs2, (${rs1})", + (CFSD FPR64:$rs2, GPCR:$rs1, 0)>; +def : InstAlias<"fld $rd, ${imm12}(${rs1})", + (CFLD FPR64:$rd, GPCR:$rs1, simm12:$imm12), 0>; +def : InstAlias<"fsd $rs2, ${imm12}(${rs1})", + (CFSD FPR64:$rs2, GPCR:$rs1, simm12:$imm12), 0>; } // Predicates = [HasCheri, HasStdExtD, IsCapMode] /// 'C' (Compressed Instructions) extension @@ -1150,6 +1160,13 @@ def : MnemonicAlias<"c.sd", "c.csd">; def : MnemonicAlias<"c.ldsp", "c.cldcsp">; def : MnemonicAlias<"c.sdsp", "c.csdcsp">; } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] +let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, + IsCapMode] in { +def : MnemonicAlias<"c.fld", "c.cfld">; +def : MnemonicAlias<"c.fsd", "c.cfsd">; +def : MnemonicAlias<"c.fldsp", "c.cfldcsp">; +def : MnemonicAlias<"c.fsdsp", "c.cfsdcsp">; +} //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns diff --git a/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s index 16d3a5630ea4..22cd8d15a8f9 100644 --- a/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s @@ -9,13 +9,25 @@ # CHECK-ASM-AND-OBJ: c.cfsd fa0, 40(ca0) # CHECK-ASM-SAME: encoding: [0x08,0xb5] c.cfsd fa0, 40(ca0) +# CHECK-ASM-AND-OBJ: c.cfsd fa0, 40(ca0) +# CHECK-ASM-SAME: encoding: [0x08,0xb5] +c.fsd fa0, 40(ca0) # CHECK-ASM-AND-OBJ: c.cfld fa0, 40(ca0) # CHECK-ASM-SAME: encoding: [0x08,0x35] c.cfld fa0, 40(ca0) +# CHECK-ASM-AND-OBJ: c.cfld fa0, 40(ca0) +# CHECK-ASM-SAME: encoding: [0x08,0x35] +c.fld fa0, 40(ca0) # CHECK-ASM-AND-OBJ: c.cfsdcsp ft1, 40(csp) # CHECK-ASM-SAME: encoding: [0x06,0xb4] c.cfsdcsp ft1, 40(csp) +# CHECK-ASM-AND-OBJ: c.cfsdcsp ft1, 40(csp) +# CHECK-ASM-SAME: encoding: [0x06,0xb4] +c.fsdsp ft1, 40(csp) # CHECK-ASM-AND-OBJ: c.cfldcsp ft1, 40(csp) # CHECK-ASM-SAME: encoding: [0xa2,0x30] c.cfldcsp ft1, 40(csp) +# CHECK-ASM-AND-OBJ: c.cfldcsp ft1, 40(csp) +# CHECK-ASM-SAME: encoding: [0xa2,0x30] +c.fldsp ft1, 40(csp) diff --git a/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s index 5c35b17f551f..8a6821100fce 100644 --- a/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s @@ -13,6 +13,12 @@ # CHECK-ASM-AND-OBJ: cfsd fa0, 40(ca0) # CHECK-ASM-SAME: encoding: [0x27,0x34,0xa5,0x02] cfsd fa0, 40(ca0) +# CHECK-ASM-AND-OBJ: cfsd fa0, 40(ca0) +# CHECK-ASM-SAME: encoding: [0x27,0x34,0xa5,0x02] +fsd fa0, 40(ca0) +# CHECK-ASM-AND-OBJ: cfld fa0, 40(ca0) +# CHECK-ASM-SAME: encoding: [0x07,0x35,0x85,0x02] +cfld fa0, 40(ca0) # CHECK-ASM-AND-OBJ: cfld fa0, 40(ca0) # CHECK-ASM-SAME: encoding: [0x07,0x35,0x85,0x02] cfld fa0, 40(ca0) @@ -20,21 +26,38 @@ cfld fa0, 40(ca0) # CHECK-ASM-AND-OBJ: cfsw ft1, 40(ca0) # CHECK-ASM-SAME: encoding: [0x27,0x24,0x15,0x02] cfsw ft1, 40(ca0) +# CHECK-ASM-AND-OBJ: cfsw ft1, 40(ca0) +# CHECK-ASM-SAME: encoding: [0x27,0x24,0x15,0x02] +fsw ft1, 40(ca0) # CHECK-ASM-AND-OBJ: cflw ft1, 40(ca0) # CHECK-ASM-SAME: encoding: [0x87,0x20,0x85,0x02] cflw ft1, 40(ca0) - +# CHECK-ASM-AND-OBJ: cflw ft1, 40(ca0) +# CHECK-ASM-SAME: encoding: [0x87,0x20,0x85,0x02] +flw ft1, 40(ca0) # CHECK-ASM-AND-OBJ: cfsd fa0, 0(ca0) # CHECK-ASM-SAME: encoding: [0x27,0x30,0xa5,0x00] cfsd fa0, (ca0) +# CHECK-ASM-AND-OBJ: cfsd fa0, 0(ca0) +# CHECK-ASM-SAME: encoding: [0x27,0x30,0xa5,0x00] +fsd fa0, (ca0) # CHECK-ASM-AND-OBJ: cfld fa0, 0(ca0) # CHECK-ASM-SAME: encoding: [0x07,0x35,0x05,0x00] cfld fa0, (ca0) +# CHECK-ASM-AND-OBJ: cfld fa0, 0(ca0) +# CHECK-ASM-SAME: encoding: [0x07,0x35,0x05,0x00] +fld fa0, (ca0) # CHECK-ASM-AND-OBJ: cfsw ft1, 0(ca0) # CHECK-ASM-SAME: encoding: [0x27,0x20,0x15,0x00] cfsw ft1, (ca0) +# CHECK-ASM-AND-OBJ: cfsw ft1, 0(ca0) +# CHECK-ASM-SAME: encoding: [0x27,0x20,0x15,0x00] +fsw ft1, (ca0) # CHECK-ASM-AND-OBJ: cflw ft1, 0(ca0) # CHECK-ASM-SAME: encoding: [0x87,0x20,0x05,0x00] cflw ft1, (ca0) +# CHECK-ASM-AND-OBJ: cflw ft1, 0(ca0) +# CHECK-ASM-SAME: encoding: [0x87,0x20,0x05,0x00] +flw ft1, (ca0)