[CHERI-RISC-V] Allow load/store mnemonics without the c prefix [2/n]

As a follow-up to the last commit this includes the aliases without an immediate offset.
CTSRD-CHERI · Aug 26, 2024 · 891cf93 · 891cf93
1 parent 9bef4d5
commit 891cf93
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Showing 4 changed files with 87 additions and 37 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
@@ -732,6 +732,13 @@ def : InstAlias<"cjalr $rs, $offset",      (CJALR       C1, GPCR:$rs, simm12:$of
 def : InstAlias<"cjalr $rd, $rs, $offset", (CJALR GPCR:$rd, GPCR:$rs, simm12:$offset), 0>;
 } // Predicates = [HasCheri, IsCapMode]
 
+// Expands to an instruction alias with and without a c prefix for loads/stores
+multiclass CPrefixedInstAlias<string Asm, dag Result> {
+  def : InstAlias<"c" # Asm, Result, 0>;
+  def : InstAlias<Asm, Result, 0>;
+}
+
+
 let Predicates = [HasCheri, IsCapMode] in {
 defm CLB  : CheriLoad_ri<0b000, "lb">;
 defm CLH  : CheriLoad_ri<0b001, "lh">;
@@ -767,12 +774,10 @@ def CSC_64  : RVInstS<0x3, OPC_STORE, (outs),
 def : InstAlias<"sc $rs2, ${imm12}(${rs1})",
                 (CSC_64  GPCR:$rs2, GPCR:$rs1, simm12:$imm12), 0>;
 
-let EmitPriority = 0 in {
-def : InstAlias<"clc $rd, (${rs1})",
-                (CLC_64  GPCR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"csc $rs2, (${rs1})",
-                (CSC_64  GPCR:$rs2, GPCR:$rs1, 0)>;
-}
+defm : CPrefixedInstAlias<"lc $rd, (${rs1})",
+                          (CLC_64  GPCR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"sc $rs2, (${rs1})",
+                          (CSC_64  GPCR:$rs2, GPCR:$rs1, 0)>;
 }
 
 let Predicates = [HasCheri, IsRV64, IsCapMode] in {
@@ -792,44 +797,29 @@ def CSC_128  : RVInstS<0x4, OPC_STORE, (outs),
 def : InstAlias<"sc $rs2, ${imm12}(${rs1})",
                 (CSC_128  GPCR:$rs2, GPCR:$rs1, simm12:$imm12), 0>;
 
-let EmitPriority = 0 in {
-def : InstAlias<"clc $rd, (${rs1})",
-                (CLC_128  GPCR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"csc $rs2, (${rs1})",
-                (CSC_128  GPCR:$rs2, GPCR:$rs1, 0)>;
-}
+defm : CPrefixedInstAlias<"lc $rd, (${rs1})",
+                          (CLC_128  GPCR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"sc $rs2, (${rs1})",
+                          (CSC_128  GPCR:$rs2, GPCR:$rs1, 0)>;
 }
 
-let EmitPriority = 0 in {
 let Predicates = [HasCheri, IsCapMode] in {
-def : InstAlias<"clb $rd, (${rs1})",
-                (CLB  GPR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"clh $rd, (${rs1})",
-                (CLH  GPR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"clw $rd, (${rs1})",
-                (CLW  GPR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"clbu $rd, (${rs1})",
-                (CLBU  GPR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"clhu $rd, (${rs1})",
-                (CLHU  GPR:$rd, GPCR:$rs1, 0)>;
-
-def : InstAlias<"csb $rs2, (${rs1})",
-                (CSB  GPR:$rs2, GPCR:$rs1, 0)>;
-def : InstAlias<"csh $rs2, (${rs1})",
-                (CSH  GPR:$rs2, GPCR:$rs1, 0)>;
-def : InstAlias<"csw $rs2, (${rs1})",
-                (CSW  GPR:$rs2, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"lb $rd, (${rs1})", (CLB  GPR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"lh $rd, (${rs1})", (CLH  GPR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"lw $rd, (${rs1})", (CLW  GPR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"lbu $rd, (${rs1})", (CLBU  GPR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"lhu $rd, (${rs1})", (CLHU  GPR:$rd, GPCR:$rs1, 0)>;
+
+defm : CPrefixedInstAlias<"sb $rs2, (${rs1})", (CSB  GPR:$rs2, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"sh $rs2, (${rs1})", (CSH  GPR:$rs2, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"sw $rs2, (${rs1})", (CSW  GPR:$rs2, GPCR:$rs1, 0)>;
 } // Predicates = [HasCheri, IsCapMode]
 
 let Predicates = [HasCheri, IsRV64, IsCapMode] in {
-def : InstAlias<"clwu $rd, (${rs1})",
-                (CLWU  GPR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"cld $rd, (${rs1})",
-                (CLD  GPR:$rd, GPCR:$rs1, 0)>;
-def : InstAlias<"csd $rs2, (${rs1})",
-                (CSD  GPR:$rs2, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"lwu $rd, (${rs1})", (CLWU  GPR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"ld $rd, (${rs1})", (CLD  GPR:$rd, GPCR:$rs1, 0)>;
+defm : CPrefixedInstAlias<"sd $rs2, (${rs1})", (CSD  GPR:$rs2, GPCR:$rs1, 0)>;
 } // Predicates = [HasCheri, IsRV64, IsCapMode]
-}
 
 /// 'A' (Atomic Instructions) extension
 

diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s
@@ -21,3 +21,16 @@ clc ca2, 17(ca0)
 # CHECK-ASM-SAME: encoding: [0xa3,0xbc,0xf6,0x00]
 csc ca5, 25(ca3)
 
+
+# CHECK-ASM-AND-OBJ: clc ca2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x03,0x36,0x05,0x00]
+clc ca2, (ca0)
+# CHECK-ASM-AND-OBJ: clc ca2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x03,0x36,0x05,0x00]
+lc ca2, (ca0)
+# CHECK-ASM-AND-OBJ: csc ca5, 0(ca3)
+# CHECK-ASM-SAME: encoding: [0x23,0xb0,0xf6,0x00]
+csc ca5, (ca3)
+# CHECK-ASM-AND-OBJ: csc ca5, 0(ca3)
+# CHECK-ASM-SAME: encoding: [0x23,0xb0,0xf6,0x00]
+sc ca5, (ca3)
diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s
@@ -50,3 +50,32 @@ clbu ra, 17(csp)
 # CHECK-ASM-AND-OBJ: clhu ra, 17(csp)
 # CHECK-ASM-SAME: encoding: [0x83,0x50,0x11,0x01]
 clhu ra, 17(csp)
+
+# CHECK-ASM-AND-OBJ:  clb a2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x03,0x06,0x05,0x00]
+clb a2, (ca0)
+# CHECK-ASM-AND-OBJ: csb a5, 0(ca3)
+# CHECK-ASM-SAME: encoding: [0x23,0x80,0xf6,0x00]
+csb a5, (ca3)
+
+# CHECK-ASM-AND-OBJ: clh a2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x03,0x16,0x05,0x00]
+clh a2, (ca0)
+# CHECK-ASM-AND-OBJ: csh a5, 0(ca3)
+# CHECK-ASM-SAME: encoding: [0x23,0x90,0xf6,0x00]
+csh a5, (ca3)
+
+# CHECK-ASM-AND-OBJ: clw ra, 0(csp)
+# CHECK-ASM-SAME: encoding: [0x83,0x20,0x01,0x00]
+clw ra, (csp)
+# CHECK-ASM-AND-OBJ: csw ra, 0(csp)
+# CHECK-ASM-SAME: encoding: [0x23,0x20,0x11,0x00]
+csw ra, (csp)
+
+# CHECK-ASM-AND-OBJ: clbu ra, 0(csp)
+# CHECK-ASM-SAME: encoding: [0x83,0x40,0x01,0x00]
+clbu ra, (csp)
+
+# CHECK-ASM-AND-OBJ: clhu ra, 0(csp)
+# CHECK-ASM-SAME: encoding: [0x83,0x50,0x01,0x00]
+clhu ra, (csp)
diff --git a/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s
@@ -31,3 +31,21 @@ csd a5, 25(ca3)
 # CHECK-ASM-AND-OBJ: clwu a2, 17(ca0)
 # CHECK-ASM-SAME: encoding: [0x03,0x66,0x15,0x01]
 clwu a2, 17(ca0)
+
+# CHECK-ASM-AND-OBJ: clc ca2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x0f,0x26,0x05,0x00]
+clc ca2, (ca0)
+# CHECK-ASM-AND-OBJ: csc ca5, 0(ca3)
+# CHECK-ASM-SAME: encoding: [0x23,0xc0,0xf6,0x00]
+csc ca5, (ca3)
+
+# CHECK-ASM-AND-OBJ: cld a2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x03,0x36,0x05,0x00]
+cld a2, (ca0)
+# CHECK-ASM-AND-OBJ: csd a5, 0(ca3)
+# CHECK-ASM-SAME: encoding: [0x23,0xb0,0xf6,0x00]
+csd a5, (ca3)
+
+# CHECK-ASM-AND-OBJ: clwu a2, 0(ca0)
+# CHECK-ASM-SAME: encoding: [0x03,0x66,0x05,0x00]
+clwu a2, (ca0)