[llvm] Fix tests based on registered targets

CTSRD-CHERI · Apr 26, 2024 · a8ecfcd · a8ecfcd
1 parent dc12882
commit a8ecfcd
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Showing 4 changed files with 5 additions and 3 deletions.
diff --git a/llvm/test/Transforms/CheriBoundAllocas/pg_lzcompress-stack-bounds-crash.ll b/llvm/test/Transforms/CheriBoundAllocas/pg_lzcompress-stack-bounds-crash.ll
@@ -1,6 +1,6 @@
 ; RUN: %cheri_purecap_opt -cheri-bound-allocas %s -o - -S -debug-only="cheri-bound-allocas" 2>&1 | %cheri_FileCheck %s -check-prefix DBG
 ; RUN: %riscv64_cheri_purecap_opt -cheri-bound-allocas %s -o - -S -debug-only="cheri-bound-allocas" 2>&1 | %cheri_FileCheck %s -check-prefix DBG
-; REQUIRES: asserts
+; REQUIRES: asserts,mips-registered-target,riscv-registered-target
 ; This crash was found compiling postgres (due to a missing depth limitation in CheriPurecapABI.cpp)
 
 target datalayout = "E-m:e-pf200:128:128:128:64-i8:8:32-i16:16:32-i64:64-n32:64-S128-A200-P200-G200"

diff --git a/llvm/test/Transforms/CheriBoundAllocas/stack-bounds-pass-load-store.ll b/llvm/test/Transforms/CheriBoundAllocas/stack-bounds-pass-load-store.ll
@@ -3,7 +3,7 @@
 ; is a single trivially rematerizable instruction so it can freely move it around to avoid stack spills.
 ; we were moving the allocation of the register that is only used later to the beginning
 
-; REQUIRES: asserts
+; REQUIRES: asserts,mips-registered-target,riscv-registered-target
 ; RUN: %cheri_purecap_opt -cheri-bound-allocas %s -o - -S -cheri-stack-bounds=if-needed -debug-only=cheri-bound-allocas 2>%t.dbg | FileCheck %s
 ; RUN: FileCheck %s -input-file=%t.dbg --check-prefixes=DBG,DBG-TYPED
 ; RUN: %cheri_purecap_opt -opaque-pointers=1 -instsimplify -cheri-bound-allocas %s -o - -S -cheri-stack-bounds=if-needed -debug-only=cheri-bound-allocas 2>%t.dbg | FileCheck %s --check-prefix=OPAQUE

diff --git a/llvm/test/Transforms/CheriBoundAllocas/stack-bounds-pass.ll b/llvm/test/Transforms/CheriBoundAllocas/stack-bounds-pass.ll
@@ -3,7 +3,7 @@
 ; is a single trivially rematerizable instruction so it can freely move it around to avoid stack spills.
 ; we were moving the allocation of the register that is only used later to the beginning
 
-; REQUIRES: asserts
+; REQUIRES: asserts,mips-registered-target,riscv-registered-target
 ; RUN: %cheri_purecap_opt -opaque-pointers=0 -cheri-bound-allocas %s -o - -S | FileCheck %s -check-prefix DEFAULT
 ; RUN: %cheri_purecap_opt -opaque-pointers=0 -cheri-bound-allocas %s -o - -S -cheri-stack-bounds-single-intrinsic-threshold=0 -cheri-stack-bounds=if-needed | FileCheck %s -check-prefix IF-NEEDED-SINGLE
 ; RUN: %cheri_purecap_opt -opaque-pointers=0 -cheri-bound-allocas %s -o - -S -cheri-stack-bounds-single-intrinsic-threshold=10 -cheri-stack-bounds=if-needed | FileCheck %s -check-prefix IF-NEEDED-PER-USE

diff --git a/llvm/test/tools/llvm-objdump/Mips/lit.local.cfg b/llvm/test/tools/llvm-objdump/Mips/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'Mips' in config.root.targets:
+    config.unsupported = True