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[CHERI-RISC-V] Allow load/store mnemonics without the c prefix #749

Merged
merged 7 commits into from
Sep 11, 2024
Merged

[CHERI-RISC-V] Allow load/store mnemonics without the c prefix #749

merged 7 commits into from
Sep 11, 2024

Commits on Aug 26, 2024

  1. [CHERI-RISC-V] Add more MC tests for loads/stores 

    We were not checking capability mode loads/stores, only
compressed ones and atomics.
    @arichardson
    arichardson committed Aug 26, 2024
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Commits on Sep 4, 2024

  1. [CHERI-RISC-V] Allow load/store mnemonics without the c prefix [1/n] 

    Instead, make it depend on the type of the operand. This commit only
touches the basic load/store instruction without the assembler aliases
or compressed instructions.
    @arichardson
    arichardson committed Sep 4, 2024
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  2. [CHERI-RISC-V] Allow load/store mnemonics without the c prefix [2/n] 

    As a follow-up to the last commit this includes the aliases without an
immediate offset.
    @arichardson
    arichardson committed Sep 4, 2024
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  3. [CHERI-RISC-V] Allow load/store mnemonics without the c prefix [3/n] 

    This adds the atomic operations
    @arichardson
    arichardson committed Sep 4, 2024
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  4. [CHERI-RISC-V] Allow load/store mnemonics without the c prefix [4/n] 

    This adds support for compressed instructions. Does not yet include Zcb
or floating-point loads/stores.
    @arichardson
    arichardson committed Sep 4, 2024
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  5. [CHERI-RISC-V] Add MC tests for floating point loads/stores

    @arichardson
    arichardson committed Sep 4, 2024
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  6. [CHERI-RISC-V] Allow load/store mnemonics without the c prefix [5/n] 

    This adds the floating point loads and stores and should conclude this
series of patches.
    @arichardson
    arichardson committed Sep 4, 2024
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