From c7c4196f1e984d5905111060c45de8c522571ec2 Mon Sep 17 00:00:00 2001 From: TheCPP Date: Sat, 12 Oct 2024 20:19:04 +0200 Subject: [PATCH] [X64] implementing the last float instruction wrappers + [FIX] fixed forgotten instruction lowering type metadata for ret --- src/CodeGen/compilation/ret.rs | 4 + src/Target/x64/asm/instr.rs | 136 ++++++++++++++++++++++++++++++--- 2 files changed, 128 insertions(+), 12 deletions(-) diff --git a/src/CodeGen/compilation/ret.rs b/src/CodeGen/compilation/ret.rs index c29a30de..585ef6e4 100644 --- a/src/CodeGen/compilation/ret.rs +++ b/src/CodeGen/compilation/ret.rs @@ -10,6 +10,8 @@ impl CompilationHelper { instr.set_out(MachineOperand::Reg(self.call.return_reg(self.arch, node.inner1.into())) ); instr.add_operand(MachineOperand::Imm(node.inner1.val() as i64)); + instr.meta = node.inner1.into(); + mc_sink.push( instr ); mc_sink.push( MachineInstr::new(MachineMnemonic::Return) ); @@ -28,6 +30,8 @@ impl CompilationHelper { super::VarLocation::Mem(stack) => instr.add_operand( MachineOperand::Stack(stack) ), } + instr.meta = node.inner1.ty; + mc_sink.push(instr); mc_sink.push( MachineInstr::new(MachineMnemonic::Return) ); diff --git a/src/Target/x64/asm/instr.rs b/src/Target/x64/asm/instr.rs index 418d07e4..8014f9e8 100644 --- a/src/Target/x64/asm/instr.rs +++ b/src/Target/x64/asm/instr.rs @@ -786,18 +786,130 @@ impl X64MCInstr { } else { todo!() } } else { todo!() } }, - Mnemonic::Movss => todo!(), - Mnemonic::Movsd => todo!(), - Mnemonic::Movups => todo!(), - Mnemonic::Movupd => todo!(), - Mnemonic::Addss => todo!(), - Mnemonic::Addsd => todo!(), - Mnemonic::Divss => todo!(), - Mnemonic::Divsd => todo!(), - Mnemonic::Mulss => todo!(), - Mnemonic::Mulsd => todo!(), - Mnemonic::Subss => todo!(), - Mnemonic::Subsd => todo!(), + Mnemonic::Movss => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movss_xmmm32_xmm, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Movss_xmm_xmmm32, (*op1).into(), op2.into())? + } else { todo!() } + } else if let Some(Operand::Mem(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movss_xmmm32_xmm, op1.into(), (*op2).into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Movsd => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movsd_xmmm64_xmm, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Movsd_xmm_xmmm64, (*op1).into(), op2.into())? + } else { todo!() } + } else if let Some(Operand::Mem(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movsd_xmmm64_xmm, op1.into(), (*op2).into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Movups => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movups_xmm_xmmm128, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Movups_xmm_xmmm128, (*op1).into(), op2.into())? + } else { todo!() } + } else if let Some(Operand::Mem(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movups_xmmm128_xmm, op1.into(), (*op2).into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Movupd => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movupd_xmm_xmmm128, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Movupd_xmm_xmmm128, (*op1).into(), op2.into())? + } else { todo!() } + } else if let Some(Operand::Mem(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Movupd_xmmm128_xmm, op1.into(), (*op2).into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Addss => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Addss_xmm_xmmm32, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Addss_xmm_xmmm32, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Addsd => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Addsd_xmm_xmmm64, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Addsd_xmm_xmmm64, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Divss => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Divss_xmm_xmmm32, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Divss_xmm_xmmm32, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Divsd => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Divsd_xmm_xmmm64, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Divsd_xmm_xmmm64, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Mulss => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Mulss_xmm_xmmm32, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Mulss_xmm_xmmm32, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Mulsd => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Mulsd_xmm_xmmm64, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Mulsd_xmm_xmmm64, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Subss => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Subss_xmm_xmmm32, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Subss_xmm_xmmm32, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, + Mnemonic::Subsd => { + if let Some(Operand::Reg(op1)) = &self.op1 { + if let Some(Operand::Reg(op2)) = &self.op2 { + Instruction::with2::(Code::Subsd_xmm_xmmm64, (*op1).into(), (*op2).into())? + } else if let Some(Operand::Mem(op2)) = &self.op2 { + Instruction::with2::(Code::Subsd_xmm_xmmm64, (*op1).into(), op2.into())? + } else { todo!() } + } else { todo!() } + }, Mnemonic::Ucomiss => todo!(), Mnemonic::Ucomisd => todo!(),