net/mlx5/hws: add support for random number match

The HW adds a random number per each hash, this value can be used for
statistic calculation over the packets, for example by setting one bit in
the mask of that field we will get half of the traffic in the flow, and
so on with the rest of the mask.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

doc/guides/nics/features/mlx5.ini

@@ -88,6 +88,7 @@ port_id              = Y
 port_representor     = Y
 ptype                = Y
 quota                = Y
+random               = Y
 tag                  = Y
 tcp                  = Y
 udp                  = Y

drivers/net/mlx5/hws/mlx5dr_definer.c

@@ -187,6 +187,7 @@ struct mlx5dr_definer_conv_data {
 	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,             rte_flow_item_esp) \
 	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,	rte_flow_item_ib_bth) \
 	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth) \
+	X(SET,		random_number,		v->value,		rte_flow_item_random) \
 	X(SET,		ib_l4_bth_a,		v->hdr.a,		rte_flow_item_ib_bth) \
 
 /* Item set function format */
@@ -2200,6 +2201,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static int
+mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd,
+				struct rte_flow_item *item,
+				int item_idx)
+{
+	const struct rte_flow_item_random *m = item->mask;
+	const struct rte_flow_item_random *l = item->last;
+	struct mlx5dr_definer_fc *fc;
+
+	if (!m)
+		return 0;
+
+	if (m->value != (m->value & UINT16_MAX)) {
+		DR_LOG(ERR, "Random value is 16 bits only");
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM];
+	fc->item_idx = item_idx;
+	fc->tag_set = &mlx5dr_definer_random_number_set;
+	fc->is_range = l && l->value;
+	DR_CALC_SET_HDR(fc, random_number, random_number);
+
+	return 0;
+}
+
 static int
 mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,
 			 struct mlx5dr_definer_fc *fc,
@@ -2251,6 +2279,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)
 	case RTE_FLOW_ITEM_TYPE_TAG:
 	case RTE_FLOW_ITEM_TYPE_META:
 	case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
+	case RTE_FLOW_ITEM_TYPE_RANDOM:
 		return 0;
 	default:
 		DR_LOG(ERR, "Range not supported over item type %d", item->type);
@@ -2645,6 +2674,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_ptype(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_PTYPE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
+			ret = mlx5dr_definer_conv_item_random(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_RANDOM;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 			ret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i);
 			item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;

drivers/net/mlx5/hws/mlx5dr_definer.h

@@ -155,6 +155,7 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,
+	MLX5DR_DEFINER_FNAME_RANDOM_NUM,
 	MLX5DR_DEFINER_FNAME_MAX,
 };
 
@@ -412,6 +413,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {
 	u8 destination_address[0x20];
 };
 
+struct mlx5_ifc_definer_hl_random_number_bits {
+	u8 random_number[0x10];
+	u8 reserved[0x10];
+};
+
 struct mlx5_ifc_definer_hl_ipv6_addr_bits {
 	u8 ipv6_address_127_96[0x20];
 	u8 ipv6_address_95_64[0x20];
@@ -521,7 +527,7 @@ struct mlx5_ifc_definer_hl_bits {
 	struct mlx5_ifc_definer_hl_mpls_bits mpls_inner;
 	u8 unsupported_config_headers_outer[0x80];
 	u8 unsupported_config_headers_inner[0x80];
-	u8 unsupported_random_number[0x20];
+	struct mlx5_ifc_definer_hl_random_number_bits random_number;
 	struct mlx5_ifc_definer_hl_ipsec_bits ipsec;
 	struct mlx5_ifc_definer_hl_metadata_bits metadata;
 	u8 unsupported_utc_timestamp[0x40];

drivers/net/mlx5/mlx5_flow.h

@@ -277,6 +277,9 @@ enum mlx5_feature_name {
 /* NSH ITEM */
 #define MLX5_FLOW_ITEM_NSH (1ull << 53)
 
+/* Random ITEM */
+#define MLX5_FLOW_ITEM_RANDOM (1ull << 54)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)