Merge pull request #120 from DUNE-DAQ/feature/fib_v2

Feature/fib v2

config/etc/addrtab/v7xx/fanout_fib_v2/ipbus_freq_ctr.xml

@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node description="Frequency counter" fwinfo="endpoint;width=1">
+	<node id="ctrl" address="0x0">
+		<node id="chan_sel" mask="0xf"/>
+		<node id="en_crap_mode" mask="0x10"/>
+	</node>
+	<node id="freq" address="0x1">
+		<node id="count" mask="0xffffff"/>
+		<node id="valid" mask="0x1000000"/>
+	</node>
+</node>

config/etc/addrtab/v7xx/fanout_fib_v2/opencores_i2c.xml

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node description="I2C master controller" fwinfo="endpoint;width=3">
+	<node id="ps_lo" address="0x0" description="Prescale low byte"/>
+	<node id="ps_hi" address="0x1" description="Prescale low byte"/>
+	<node id="ctrl" address="0x2" description="Control"/>
+	<node id="data" address="0x3" description="Data"/>
+	<node id="cmd_stat" address="0x4" description="Command / status"/>
+</node>

config/etc/addrtab/v7xx/fanout_fib_v2/pdts_ep_mon.xml

@@ -0,0 +1,26 @@
+<node id="ep_core" description="PDTS endpoint core wrapper" fwinfo="endpoint" class="EndpointNode">
+		<node id="csr" address="0x0" fwinfo="endpoint;width=1">
+			<node id="ctrl" address="0x0">
+				<node id="ep_en" mask="0x1"/>
+				<node id="ctr_rst" mask="0x2"/>
+				<node id="addr" mask="0xffff0000"/>
+			</node>
+			<node id="stat" address="0x1">
+				<node id="ep_stat" mask="0x0f"/>
+				<node id="ep_rdy" mask="0x10"/>
+				<node id="ep_txen" mask="0x20"/>
+				<node id="ctrs_rdy" mask="0x40"/>
+			</node>
+		</node>
+		<node id="tstamp" address="0x2" mode="block" size="0x2" fwinfo="endpoint;width=1"/>
+		<node id="cmd_ctrs" address="0x4" fwinfo="endpoint;width=1">
+			<node id="addr" address="0x0"/>
+			<node id="data" address="0x1" size="0x100" mode="port"/>
+		</node>
+		<node id="cmd_log" address="0x8" fwinfo="endpoint;width=2">
+			<node id="tstamp_l" address="0x0"/>
+			<node id="tstamp_h" address="0x1"/>
+			<node id="cmd" address="0x2"/>
+		</node>
+		<node id="dcmd_ctrs" address="0x10" mode="block" size="0x8" fwinfo="endpoint;width=3"/>
+</node>

config/etc/addrtab/v7xx/fanout_fib_v2/pdts_fib_v2_io.xml

@@ -0,0 +1,39 @@
+<node id="io" description="FIB V2 IO" fwinfo="endpoint" class="FIBV2IONode">
+		<node id="csr" address="0x0" description="ctrl/stat register" fwinfo="endpoint;width=1">
+				<node id="ctrl" address="0x0">
+					<node id="soft_rst" mask="0x1"/>
+					<node id="nuke" mask="0x2"/>
+					<node id="rst" mask="0x4"/>
+					<node id="clk_select" mask="0x8"/>
+					<node id="clk_enable" mask="0x10"/>
+					<node id="sfp_tx_disable" mask="0xff00"/>
+					<node id="bp_tx_edge" mask="0x10000"/>
+					<node id="sfp_tx_edge" mask="0x20000"/>
+				</node>
+				<node id="stat" address="0x1">
+					<node id="mmcm_ok" mask="0x1"/>
+					<node id="pll_ok" mask="0x2"/>
+					<node id="mmcm_sticky" mask="0x4"/>
+					<node id="pll_sticky" mask="0x8"/>
+					<node id="sfp_los" mask="0xff00"/>
+					<node id="sfp_fault" mask="0xff0000"/>
+				</node>
+		</node>
+		<node id="config" address="0x2" description="board/firmware config" fwinfo="endpoint;width=1">
+		    <node id="no_cdr" mask="0xff000000"/>
+		    <node id="board_type" mask="0xff0000"/>
+		    <node id="carrier_type" mask="0xff00"/>
+		    <node id="design_type" mask="0xff"/>
+		    <node id="clock_frequency" address="0x1" mask="0xffffffff"/>
+		</node>
+		<node id="i2c" address="0x08" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="UID_PROM=0x50;SI5345=0x68;Expander1=0x74;Expander2=0x75;AX3_Switch=0x21"/>
+		<node id="i2c_sfp0" address="0x10" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="i2c_sfp1" address="0x18" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="i2c_sfp2" address="0x20" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="i2c_sfp3" address="0x28" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="i2c_sfp4" address="0x30" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="i2c_sfp5" address="0x38" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="i2c_sfp6" address="0x40" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="i2c_sfp7" address="0x48" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
+		<node id="freq" address="0x50" module="file://ipbus_freq_ctr.xml" class="FrequencyCounterNode"/>
+</node>

config/etc/addrtab/v7xx/fanout_fib_v2/pdts_upstream_cdr.xml

@@ -0,0 +1,12 @@
+<node id="upstream_cdr" description="CDR block for upstream rx" fwinfo="endpoint;width=1" class="UpstreamCDRNode">
+	<node id="ctrl" address="0x0">
+		<node id="resync" mask="0x1"/>
+	</node>
+	<node id="stat" address="0x1">
+		<node id="locked" mask="0x1"/>
+		<node id="los" mask="0x2"/>
+		<node id="phase" mask="0x70"/>
+		<node id="err" mask="0x80"/>
+		<node id="valid" mask="0xff00"/>
+	</node>
+</node>

config/etc/addrtab/v7xx/fanout_fib_v2/pdts_upstream_mux.xml

@@ -0,0 +1,7 @@
+<node id="pdts_upstream_mux" description="Switch between different downstream timing sources and pass upstream" fwinfo="endpoint">
+		<node id="csr" address="0x0" fwinfo="endpoint;width=0">
+			<node id="ctrl" address="0x0">
+				<node id="src" mask="0x7"/>
+			</node>
+		</node>
+</node>

config/etc/addrtab/v7xx/fanout_fib_v2/top_fib_v2.xml

@@ -0,0 +1,13 @@
+<node id="TOP" class="FanoutDesign">
+    <node id="io" address="0x0" module="file://pdts_fib_v2_io.xml"/>
+    <node id="endpoint0" address="0x100" module="file://pdts_ep_mon.xml"/>
+    <node id="us_mux" address="0x400" module="file://pdts_upstream_mux.xml"/>
+    <node id="cdr0" address="0x0600" module="file://pdts_upstream_cdr.xml"/>
+    <node id="cdr1" address="0x0800" module="file://pdts_upstream_cdr.xml"/>
+    <node id="cdr2" address="0x0A00" module="file://pdts_upstream_cdr.xml"/>
+    <node id="cdr3" address="0x0C00" module="file://pdts_upstream_cdr.xml"/>
+    <node id="cdr4" address="0x0E00" module="file://pdts_upstream_cdr.xml"/>
+    <node id="cdr5" address="0x1000" module="file://pdts_upstream_cdr.xml"/>
+    <node id="cdr6" address="0x1200" module="file://pdts_upstream_cdr.xml"/>
+    <node id="cdr7" address="0x1400" module="file://pdts_upstream_cdr.xml"/>
+</node>

include/timing/CDCLVD110Node.hpp

@@ -0,0 +1,54 @@
+/**
+ * @file CDCLVD110Node.hpp
+ *
+ * CDCLVD110Node is a class providing an interface
+ * to the physical CDCLVD110 IC.
+ *
+ * This is part of the DUNE DAQ Software Suite, copyright 2020.
+ * Licensing/copyright details are in the COPYING file that you should have
+ * received with this code.
+ */
+
+#ifndef TIMING_INCLUDE_TIMING_CDCLVD110NODE_HPP_
+#define TIMING_INCLUDE_TIMING_CDCLVD110NODE_HPP_
+
+#include "timing/ClockGeneratorInterface.hpp"
+
+#include "timing/timinghardwareinfo/Structs.hpp"
+#include "timing/timinghardwareinfo/Nljs.hpp"
+
+#include "ers/Issue.hpp"
+
+#include <string>
+
+namespace dunedaq {
+namespace timing {
+
+/**
+ * @class      CDCLVD110Node
+ *
+ * @brief      uhal::Node implementing CDCLVD110 interface
+ */
+class CDCLVD110Node
+  : public ClockGeneratorInterface
+{
+  UHAL_DERIVEDNODE(CDCLVD110Node)
+public:
+  explicit CDCLVD110Node(const uhal::Node& node);
+  virtual ~CDCLVD110Node();
+
+  /**
+   * @brief     Get status string, optionally print.
+   */
+  std::string get_status(bool print_out = false) const override;
+
+  /**
+   * @brief     Get status string, optionally print.
+   */
+  void get_info(timinghardwareinfo::TimingPLLMonitorData& mon_data) const override;
+};
+
+} // namespace timing
+} // namespace dunedaq
+
+#endif // TIMING_INCLUDE_TIMING_CDCLVD110NODE_HPP_

include/timing/ClockGeneratorInterface.hpp

@@ -0,0 +1,47 @@
+/**
+ * @file ClockGeneratorInterface.hpp
+ *
+ * ClockGeneratorInterface is a class providing an interface
+ * to the physical CDCLVD110 IC.
+ *
+ * This is part of the DUNE DAQ Software Suite, copyright 2020.
+ * Licensing/copyright details are in the COPYING file that you should have
+ * received with this code.
+ */
+
+#ifndef TIMING_INCLUDE_TIMING_CLOCKGENERATORINTERFACE_HPP_
+#define TIMING_INCLUDE_TIMING_CLOCKGENERATORINTERFACE_HPP_
+
+#include "timing/TimingNode.hpp"
+
+#include "timing/timinghardwareinfo/Structs.hpp"
+#include "timing/timinghardwareinfo/Nljs.hpp"
+
+#include "ers/Issue.hpp"
+
+#include <string>
+
+namespace dunedaq {
+namespace timing {
+
+/**
+ * @class      ClockGeneratorInterface
+ *
+ * @brief      uhal::Node implementing clock gen. interface
+ */
+class ClockGeneratorInterface : public TimingNode
+{
+public:
+  explicit ClockGeneratorInterface(const uhal::Node& node) : TimingNode(node) {}
+  virtual ~ClockGeneratorInterface() {}
+
+  /**
+   * @brief     Get status string, optionally print.
+   */
+  virtual void get_info(timinghardwareinfo::TimingPLLMonitorData& mon_data) const = 0;
+};
+
+} // namespace timing
+} // namespace dunedaq
+
+#endif // TIMING_INCLUDE_TIMING_CLOCKGENERATORINTERFACE_HPP_

include/timing/FIBIONode.hpp

@@ -111,7 +111,7 @@ class FIBIONode : public SFPMuxIONode {
     /**
      * @brief      Switch on or off the SFP tx laser via the I2C IO expander controlling the sfp tx disable pin. aOn=1: laster transmitting, tx disable pin = 0; aOn=0: laster NOT transmitting, tx disable pin = 1. 
      */
-    void switch_sfp_tx(uint32_t sfp_id, bool turn_on) const; // NOLINT(build/unsigned)
+    void switch_sfp_tx(uint32_t sfp_id, bool turn_on) const override; // NOLINT(build/unsigned)
 
     // /**
     // * @brief      Fill hardware monitoring structure.

include/timing/FIBV2IONode.hpp

@@ -0,0 +1,124 @@
+/**
+ * @file FIBV2IONode.hpp
+ *
+ * FMCIONode is a class providing an interface
+ * to the FIB IO firmware block.
+ *
+ * This is part of the DUNE DAQ Software Suite, copyright 2020.
+ * Licensing/copyright details are in the COPYING file that you should have
+ * received with this code.
+ */
+
+#ifndef TIMING_INCLUDE_TIMING_FIBV2IONODE_HPP_
+#define TIMING_INCLUDE_TIMING_FIBV2IONODE_HPP_
+
+// Timing Headers
+#include "timing/IONode.hpp"
+#include "timing/CDCLVD110Node.hpp"
+#include "timing/TimingIssues.hpp"
+
+#include "logging/Logging.hpp"
+
+// uHal Headers
+#include "uhal/DerivedNode.hpp"
+
+// C++ Headers
+#include <chrono>
+#include <string>
+
+namespace dunedaq {
+namespace timing {
+
+/**
+ * @brief      Class for the FIB board.
+ */
+class FIBV2IONode : public IONode {
+    UHAL_DERIVEDNODE(FIBV2IONode)
+
+public:
+    explicit FIBV2IONode(const uhal::Node& aNode);
+    virtual ~FIBV2IONode();
+
+    /**
+     * @brief      Get the UID address parameter name.
+     *
+     * @return     { description_of_the_return_value }
+     */
+    std::string get_uid_address_parameter_name() const override;
+
+    /**
+     * @brief     Get status string, optionally print.
+     */
+    std::string get_status(bool print_out=false) const override;
+
+    /**
+     * @brief      Reset IO, with clock file look up.
+     */
+    void reset(const ClockSource& clock_source) const override;
+
+    /**
+     * @brief      Print status of on-board SFP.
+     */
+    std::string get_sfp_status(uint32_t sfp_id, bool print_out=false) const override; // NOLINT(build/unsigned)
+
+    /**
+     * @brief      control tx laser of on-board SFP softly (I2C command)
+     */
+    void switch_sfp_soft_tx_control_bit(uint32_t sfp_id, bool turn_on) const override; // NOLINT(build/unsigned)
+
+    /**
+     * @brief      Switch on or off the SFP tx laser via the I2C IO expander controlling the sfp tx disable pin. aOn=1: laster transmitting, tx disable pin = 0; aOn=0: laster NOT transmitting, tx disable pin = 1. 
+     */
+    void switch_sfp_tx(uint32_t sfp_id, bool turn_on) const override; // NOLINT(build/unsigned)
+
+    /**
+      * @brief      Print status of on-board PLL.
+      */
+    std::string get_pll_status(bool print_out = false) const override {return "No status yet for CDCLVD110 on FIBv2";};
+
+    void get_info(timinghardwareinfo::TimingPLLMonitorData& mon_data) const override;
+
+    ///**
+    // * @brief      Get the PLL chip.
+    // *
+    // * @return     { description_of_the_return_value }
+    // */
+    //std::unique_ptr<const CDCLVD110Node> get_pll() const;
+
+    // /**
+    // * @brief      Fill hardware monitoring structure.
+    // */
+    // void get_info(timinghardwareinfo::TimingFIBMonitorData& mon_data) const;
+
+    // /**
+    //  * @brief    Give info to collector.
+    //  */
+    // void get_info(opmonlib::InfoCollector& ci, int level) const override;
+
+private:
+
+    void validate_sfp_id(uint32_t sfp_id) const; // NOLINT(build/unsigned)
+
+    /**
+     * @brief      No config file for FIB v2
+     */
+    void reset(const std::string& clock_config_file) const override {}
+
+    /**
+      * @brief      Get the PLL chip.
+      *
+      * @return     { description_of_the_return_value }
+      */
+    std::unique_ptr<const SI534xSlave> get_pll() const override {return nullptr;}
+
+    /**
+     * @brief      Configure clock chip.
+     */
+    void configure_pll(const std::string& clock_config_file = "") const override  {TLOG() << "No text config for CDCLVD110";}
+
+};
+
+} // namespace timing
+} // namespace dunedaq
+
+#endif // TIMING_INCLUDE_TIMING_FIBV2IONODE_HPP_

include/timing/FMCIONode.hpp

@@ -69,6 +69,11 @@ class FMCIONode : public IONode
     */
   std::string get_clock_frequencies_table(bool print_out = false) const override;
 
+  /**
+   * @brief      control tx laser of on-board SFP
+   */
+  void switch_sfp_tx(uint32_t sfp_id, bool turn_on) const override; // NOLINT(build/unsigned)
+
   // /**
   //  * @brief      Fill hardware monitoring structure.
   //  */
@@ -78,6 +83,8 @@ class FMCIONode : public IONode
   //  * @brief    Give info to collector.
   //  */
   // void get_info(opmonlib::InfoCollector& ci, int level) const override;
+private:
+  void validate_sfp_id(uint32_t sfp_id) const; // NOLINT(build/unsigned)
 };
 
 } // namespace timing

include/timing/GIBIONode.hpp

@@ -79,6 +79,11 @@ class GIBIONode : public IONode
    */
   void switch_sfp_soft_tx_control_bit(uint32_t sfp_id, bool turn_on) const override; // NOLINT(build/unsigned)
 
+  /**
+   * @brief      control tx laser of on-board SFP softly (I2C command)
+   */
+  void switch_sfp_tx(uint32_t sfp_id, bool turn_on) const override; // NOLINT(build/unsigned)
+
   /**
    * @brief      Fill hardware monitoring structure.
    */