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chess_module.syr
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.00 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.00 secs
-->
Reading design: chess_module.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "chess_module.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "chess_module"
Output Format : NGC
Target Device : xc6slx9-3-tqg144
---- Source Options
Top Module Name : chess_module
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
---- Other Options
Cores Search Directories : {"ipcore_dir" }
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "/home/ise/Shared/VHDL_CHESS_Project/ipcore_dir/clock_generator.v" into library work
Parsing module <clock_generator>.
Parsing VHDL file "/home/ise/Shared/VHDL_CHESS_Project/VGAsync_controller.vhd" into library work
Parsing entity <VGAsync_controller>.
Parsing architecture <Behavioral> of entity <vgasync_controller>.
Parsing VHDL file "/home/ise/Shared/VHDL_CHESS_Project/path_check.vhd" into library work
Parsing entity <path_check>.
Parsing architecture <Behavioral> of entity <path_check>.
Parsing VHDL file "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" into library work
Parsing entity <chess_logic_module>.
INFO:HDLCompiler:1676 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 10. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
INFO:HDLCompiler:1676 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 11. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
INFO:HDLCompiler:1676 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 18. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
INFO:HDLCompiler:1676 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 19. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
INFO:HDLCompiler:1676 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 22. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
INFO:HDLCompiler:1676 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 26. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
Parsing architecture <Behavioral> of entity <chess_logic_module>.
Parsing VHDL file "/home/ise/Shared/VHDL_CHESS_Project/chess_display_controller.vhd" into library work
Parsing entity <chess_display_controller>.
Parsing architecture <Behavioral> of entity <chess_display_controller>.
Parsing VHDL file "/home/ise/Shared/VHDL_CHESS_Project/button_debounce.vhd" into library work
Parsing entity <button_debounce>.
Parsing architecture <Behavioral> of entity <button_debounce>.
Parsing VHDL file "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" into library work
Parsing entity <chess_module>.
Parsing architecture <Behavioral> of entity <chess_module>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <chess_module> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:89 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 115: <bufg> remains a black-box since it has no binding entity.
Going to verilog side to elaborate module clock_generator
Elaborating module <clock_generator>.
Elaborating module <BUFG>.
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=1,CLKFX_MULTIPLY=5,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=50.0,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="1X",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/ise/Shared/VHDL_CHESS_Project/ipcore_dir/clock_generator.v" Line 130: Assignment to status_int ignored, since the identifier is never used
Back to vhdl to continue elaboration
Elaborating entity <button_debounce> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:439 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 127: Formal port board_out_addr of mode buffer cannot be associated with actual port board_out_addr of mode out
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 10. board_out_addr is declared here
WARNING:HDLCompiler:439 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 128: Formal port board_out_piece of mode buffer cannot be associated with actual port board_out_piece of mode out
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 11. board_out_piece is declared here
WARNING:HDLCompiler:439 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 135: Formal port cursor_addr of mode buffer cannot be associated with actual port cursor_addr of mode out
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 18. cursor_addr is declared here
WARNING:HDLCompiler:439 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 136: Formal port selected_addr of mode buffer cannot be associated with actual port selected_addr of mode out
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 19. selected_addr is declared here
WARNING:HDLCompiler:439 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 139: Formal port move_is_legal of mode buffer cannot be associated with actual port move_is_legal of mode out
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 22. move_is_legal is declared here
WARNING:HDLCompiler:439 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 143: Formal port promotion_piece of mode buffer cannot be associated with actual port promotion_piece of mode out
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 26. promotion_piece is declared here
Elaborating entity <chess_logic_module> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:321 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 265: Comparison between arrays of unequal length always returns FALSE.
INFO:HDLCompiler:679 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 344. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 152: Assignment to king_captured ignored, since the identifier is never used
Elaborating entity <path_check> (architecture <Behavioral>) from library <work>.
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 10. board_out_addr is declared here
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 11. board_out_piece is declared here
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 18. cursor_addr is declared here
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 19. selected_addr is declared here
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 22. move_is_legal is declared here
INFO:HDLCompiler:1408 - "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd" Line 26. promotion_piece is declared here
Elaborating entity <chess_display_controller> (architecture <Behavioral>) from library <work>.
Elaborating entity <VGAsync_controller> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:92 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" Line 316: reset should be on the sensitivity list of the process
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <chess_module>.
Related source file is "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd".
INFO:Xst:3210 - "/home/ise/Shared/VHDL_CHESS_Project/chess_module.vhd" line 194: Output port <LOCKED> of the instance <clk_gen_inst> is unconnected or connected to loadless signal.
Found 1-bit register for signal <BtnC_prev>.
Found 1-bit register for signal <BtnC_edge>.
Found 256-bit register for signal <board>.
Found 27-bit register for signal <DIV_CLK>.
Found 27-bit adder for signal <DIV_CLK[26]_GND_4_o_add_0_OUT> created at line 1241.
Found 8-bit adder for signal <n0300> created at line 322.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 285 D-type flip-flop(s).
inferred 256 Multiplexer(s).
Unit <chess_module> synthesized.
Synthesizing Unit <clock_generator>.
Related source file is "/home/ise/Shared/VHDL_CHESS_Project/ipcore_dir/clock_generator.v".
Summary:
no macro.
Unit <clock_generator> synthesized.
Synthesizing Unit <button_debounce>.
Related source file is "/home/ise/Shared/VHDL_CHESS_Project/button_debounce.vhd".
Found 1-bit register for signal <Btn_pulse>.
Found 3-bit register for signal <state>.
Found 14-bit register for signal <I>.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 5 |
| Transitions | 11 |
| Inputs | 2 |
| Outputs | 4 |
| Clock | CLK (rising_edge) |
| Reset | RESET (positive) |
| Reset type | asynchronous |
| Reset State | init |
| Power Up State | init |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 14-bit adder for signal <I[13]_GND_9_o_add_9_OUT> created at line 1241.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 15 D-type flip-flop(s).
inferred 6 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <button_debounce> synthesized.
Synthesizing Unit <chess_logic_module>.
Related source file is "/home/ise/Shared/VHDL_CHESS_Project/chess_logic_module.vhd".
Found 1-bit register for signal <player_to_move>.
Found 1-bit register for signal <board_change_enable>.
Found 6-bit register for signal <board_out_addr>.
Found 4-bit register for signal <board_out_piece>.
Found 2-bit register for signal <promotion_piece>.
Found 3-bit register for signal <current_state>.
Found 6-bit register for signal <cursor_addr_internal>.
Found 6-bit register for signal <selected_addr_internal>.
Found finite state machine <FSM_1> for signal <current_state>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 28 |
| Inputs | 10 |
| Outputs | 5 |
| Clock | CLK (rising_edge) |
| Reset | RESET (positive) |
| Reset type | asynchronous |
| Reset State | 000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 6-bit adder for signal <board_out_addr[5]_GND_10_o_add_83_OUT> created at line 1241.
Found 6-bit adder for signal <cursor_addr_internal[5]_GND_10_o_add_128_OUT> created at line 1241.
Found 6-bit adder for signal <cursor_addr_internal[5]_GND_10_o_add_132_OUT> created at line 1241.
Found 6-bit adder for signal <selected_addr_internal[5]_GND_10_o_add_175_OUT> created at line 1241.
Found 6-bit adder for signal <selected_addr_internal[5]_GND_10_o_add_180_OUT> created at line 1241.
Found 3-bit adder for signal <selected_addr_internal[5]_GND_10_o_add_185_OUT> created at line 1241.
Found 3-bit subtractor for signal <GND_10_o_GND_10_o_sub_7_OUT<2:0>> created at line 126.
Found 3-bit subtractor for signal <GND_10_o_GND_10_o_sub_8_OUT<2:0>> created at line 128.
Found 3-bit subtractor for signal <GND_10_o_GND_10_o_sub_11_OUT<2:0>> created at line 133.
Found 3-bit subtractor for signal <GND_10_o_GND_10_o_sub_12_OUT<2:0>> created at line 135.
Found 6-bit subtractor for signal <GND_10_o_GND_10_o_sub_127_OUT<5:0>> created at line 1308.
Found 6-bit subtractor for signal <GND_10_o_GND_10_o_sub_131_OUT<5:0>> created at line 1308.
Found 6-bit subtractor for signal <GND_10_o_GND_10_o_sub_157_OUT<5:0>> created at line 1308.
Found 6-bit subtractor for signal <GND_10_o_GND_10_o_sub_162_OUT<5:0>> created at line 1308.
Found 3-bit subtractor for signal <GND_10_o_GND_10_o_sub_167_OUT<2:0>> created at line 1308.
Found 64x4-bit Read Only RAM for signal <board_out_addr[5]_GND_10_o_wide_mux_81_OUT>
Found 4-bit 64-to-1 multiplexer for signal <cursor_contents> created at line 148.
Found 4-bit 64-to-1 multiplexer for signal <selected_contents> created at line 149.
Found 4-bit 64-to-1 multiplexer for signal <n0437> created at line 392.
Found 4-bit 64-to-1 multiplexer for signal <n0441> created at line 410.
Found 1-bit 8-to-1 multiplexer for signal <move_legal> created at line 385.
Found 3-bit comparator lessequal for signal <n0005> created at line 125
Found 3-bit comparator lessequal for signal <n0010> created at line 132
Found 4-bit comparator equal for signal <player_to_move_board_out_piece[3]_equal_104_o> created at line 255
Found 3-bit comparator greater for signal <selected_addr_internal[2]_cursor_addr_internal[2]_LessThan_115_o> created at line 325
Found 6-bit comparator equal for signal <cursor_addr_internal[5]_GND_10_o_equal_158_o> created at line 393
Found 6-bit comparator equal for signal <cursor_addr_internal[5]_GND_10_o_equal_163_o> created at line 397
Found 3-bit comparator equal for signal <cursor_addr_internal[5]_GND_10_o_equal_168_o> created at line 402
Found 6-bit comparator equal for signal <cursor_addr_internal[5]_selected_addr_internal[5]_equal_177_o> created at line 411
Found 6-bit comparator equal for signal <cursor_addr_internal[5]_selected_addr_internal[5]_equal_182_o> created at line 415
Found 3-bit comparator equal for signal <cursor_addr_internal[5]_selected_addr_internal[5]_equal_187_o> created at line 420
Found 4-bit comparator equal for signal <h_delta[3]_v_delta[3]_equal_197_o> created at line 455
Found 4-bit comparator lessequal for signal <n0243> created at line 463
Found 4-bit comparator lessequal for signal <n0245> created at line 463
Summary:
inferred 1 RAM(s).
inferred 12 Adder/Subtractor(s).
inferred 26 D-type flip-flop(s).
inferred 13 Comparator(s).
inferred 52 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <chess_logic_module> synthesized.
Synthesizing Unit <path_check>.
Related source file is "/home/ise/Shared/VHDL_CHESS_Project/path_check.vhd".
Found 7-bit subtractor for signal <n1110[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1112[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1114[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1116[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1118[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1120[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1122[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1124[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1126[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1128[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1130[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1132[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1134[6:0]> created at line 57.
Found 7-bit subtractor for signal <n1136[6:0]> created at line 57.
Found 7-bit adder for signal <n1439> created at line 47.
Found 7-bit adder for signal <n1441> created at line 47.
Found 7-bit adder for signal <n1443> created at line 47.
Found 7-bit adder for signal <n1445> created at line 47.
Found 7-bit adder for signal <n1447> created at line 47.
Found 7-bit adder for signal <n1449> created at line 47.
Found 7-bit adder for signal <n1451> created at line 47.
Found 7-bit adder for signal <n1453> created at line 47.
Found 7-bit adder for signal <n1455> created at line 47.
Found 7-bit adder for signal <n1457> created at line 47.
Found 7-bit adder for signal <n1459> created at line 47.
Found 7-bit adder for signal <n1461> created at line 47.
Found 7-bit adder for signal <n1463> created at line 47.
Found 7-bit adder for signal <n1465> created at line 47.
Found 6-bit adder for signal <selected_addr[5]_GND_17_o_add_246_OUT> created at line 72.
Found 6-bit adder for signal <selected_addr[5]_GND_17_o_add_252_OUT> created at line 72.
Found 6-bit adder for signal <selected_addr[5]_PWR_13_o_add_258_OUT> created at line 72.
Found 6-bit adder for signal <selected_addr[5]_PWR_13_o_add_264_OUT> created at line 72.
Found 6-bit adder for signal <selected_addr[5]_PWR_13_o_add_270_OUT> created at line 72.
Found 6-bit adder for signal <selected_addr[5]_PWR_13_o_add_276_OUT> created at line 72.
Found 7-bit adder for signal <n1150> created at line 72.
Found 7-bit adder for signal <n1152> created at line 72.
Found 7-bit adder for signal <n1154> created at line 72.
Found 7-bit adder for signal <n1156> created at line 72.
Found 7-bit adder for signal <n1158> created at line 72.
Found 7-bit adder for signal <n1160> created at line 72.
Found 7-bit adder for signal <n1162> created at line 72.
Found 7-bit adder for signal <n1190> created at line 98.
Found 7-bit adder for signal <n1192> created at line 98.
Found 7-bit adder for signal <n1194> created at line 98.
Found 7-bit adder for signal <n1196> created at line 98.
Found 7-bit adder for signal <n1198> created at line 98.
Found 7-bit adder for signal <n1200> created at line 98.
Found 7-bit adder for signal <n1202> created at line 98.
Found 7-bit adder for signal <n1204> created at line 98.
Found 7-bit adder for signal <n1206> created at line 98.
Found 7-bit adder for signal <n1208> created at line 98.
Found 7-bit adder for signal <n1210> created at line 98.
Found 7-bit adder for signal <n1212> created at line 98.
Found 7-bit adder for signal <n1214> created at line 98.
Found 7-bit adder for signal <n1216> created at line 98.
Found 7-bit adder for signal <n1246> created at line 120.
Found 7-bit adder for signal <n1248> created at line 120.
Found 7-bit adder for signal <n1250> created at line 120.
Found 7-bit adder for signal <n1252> created at line 120.
Found 7-bit adder for signal <n1254> created at line 120.
Found 7-bit adder for signal <n1256> created at line 120.
Found 7-bit adder for signal <n1258> created at line 120.
Found 8-bit adder for signal <n1260> created at line 120.
Found 8-bit adder for signal <n1262> created at line 120.
Found 8-bit adder for signal <n1264> created at line 120.
Found 8-bit adder for signal <n1266> created at line 120.
Found 8-bit adder for signal <n1268> created at line 120.
Found 8-bit adder for signal <n1270> created at line 120.
Found 8-bit adder for signal <n1272> created at line 120.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_379_OUT<5:0>> created at line 82.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_385_OUT<5:0>> created at line 82.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_391_OUT<5:0>> created at line 82.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_397_OUT<5:0>> created at line 82.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_403_OUT<5:0>> created at line 82.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_361_OUT<5:0>> created at line 82.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_373_OUT<5:0>> created at line 82.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_513_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_520_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_527_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_534_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_541_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_548_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_555_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_569_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_576_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_583_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_590_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_597_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_604_OUT<5:0>> created at line 108.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_711_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_718_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_725_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_732_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_739_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_746_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_753_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_767_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_774_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_781_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_788_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_795_OUT<5:0>> created at line 130.
Found 6-bit subtractor for signal <GND_17_o_GND_17_o_sub_802_OUT<5:0>> created at line 130.
Found 4-bit 64-to-1 multiplexer for signal <n1083> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1085> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1087> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1089> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1091> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1093> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1095> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1097> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1099> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1101> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1103> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1105> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1107> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1109> created at line 48.
Found 4-bit 64-to-1 multiplexer for signal <n1111> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1113> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1115> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1117> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1119> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1121> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1123> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1125> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1127> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1129> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1131> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1133> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1135> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1137> created at line 58.
Found 4-bit 64-to-1 multiplexer for signal <n1139> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1141> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1143> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1145> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1147> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1149> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1151> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1153> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1155> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1157> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1159> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1161> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1163> created at line 73.
Found 4-bit 64-to-1 multiplexer for signal <n1165> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1167> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1169> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1171> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1173> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1175> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1177> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1179> created at line 83.
Found 4-bit 64-to-1 multiplexer for signal <n1191> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1193> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1195> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1197> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1199> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1201> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1203> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1205> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1207> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1209> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1211> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1213> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1215> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1217> created at line 99.
Found 4-bit 64-to-1 multiplexer for signal <n1219> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1221> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1223> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1225> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1227> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1229> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1231> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1235> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1237> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1239> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1241> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1243> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1245> created at line 109.
Found 4-bit 64-to-1 multiplexer for signal <n1247> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1249> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1251> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1253> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1255> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1257> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1259> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1261> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1263> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1265> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1267> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1269> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1271> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1273> created at line 121.
Found 4-bit 64-to-1 multiplexer for signal <n1275> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1277> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1279> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1281> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1283> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1285> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1287> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1291> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1293> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1295> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1297> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1299> created at line 131.
Found 4-bit 64-to-1 multiplexer for signal <n1301> created at line 131.
Found 4-bit comparator greater for signal <GND_17_o_h_delta[3]_LessThan_66_o> created at line 42
Found 3-bit comparator greater for signal <selected_addr[2]_cursor_addr[2]_LessThan_67_o> created at line 43
Found 4-bit comparator lessequal for signal <n0185> created at line 56
Found 4-bit comparator lessequal for signal <n0195> created at line 56
Found 4-bit comparator lessequal for signal <n0205> created at line 56
Found 4-bit comparator lessequal for signal <n0215> created at line 56
Found 4-bit comparator lessequal for signal <n0225> created at line 56
Found 4-bit comparator lessequal for signal <n0235> created at line 56
Found 4-bit comparator lessequal for signal <n0245> created at line 56
Found 4-bit comparator lessequal for signal <n0255> created at line 56
Found 4-bit comparator lessequal for signal <n0265> created at line 56
Found 4-bit comparator lessequal for signal <n0275> created at line 56
Found 4-bit comparator lessequal for signal <n0285> created at line 56
Found 4-bit comparator lessequal for signal <n0295> created at line 56
Found 4-bit comparator lessequal for signal <n0305> created at line 56
Found 4-bit comparator greater for signal <GND_17_o_v_delta[3]_LessThan_238_o> created at line 67
Found 3-bit comparator greater for signal <selected_addr[5]_cursor_addr[5]_LessThan_239_o> created at line 68
Found 4-bit comparator lessequal for signal <n0431> created at line 81
Found 4-bit comparator lessequal for signal <n0441> created at line 81
Found 4-bit comparator lessequal for signal <n0451> created at line 81
Found 4-bit comparator lessequal for signal <n0461> created at line 81
Found 4-bit comparator lessequal for signal <n0471> created at line 81
Found 4-bit comparator lessequal for signal <n0481> created at line 81
Found 4-bit comparator lessequal for signal <n0491> created at line 81
Found 4-bit comparator lessequal for signal <n0501> created at line 81
Found 4-bit comparator lessequal for signal <n0511> created at line 81
Found 4-bit comparator lessequal for signal <n0521> created at line 81
Found 4-bit comparator lessequal for signal <n0531> created at line 81
Found 4-bit comparator lessequal for signal <n0541> created at line 81
Found 4-bit comparator lessequal for signal <n0551> created at line 81
Found 4-bit comparator equal for signal <h_delta[3]_v_delta[3]_equal_409_o> created at line 92
Summary:
inferred 102 Adder/Subtractor(s).
inferred 31 Comparator(s).
inferred 327 Multiplexer(s).
Unit <path_check> synthesized.
Synthesizing Unit <chess_display_controller>.
Related source file is "/home/ise/Shared/VHDL_CHESS_Project/chess_display_controller.vhd".
Found 8-bit register for signal <output_color>.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_69_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_71_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_73_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_75_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_77_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_79_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_81_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_82_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_99_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_101_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_103_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_105_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_107_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_109_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_111_OUT<6:0>> created at line 1308.
Found 7-bit subtractor for signal <GND_19_o_GND_19_o_sub_112_OUT<6:0>> created at line 1308.
Found 1-bit 8-to-1 multiplexer for signal <art_x[2]_art_y[2]_Mux_177_o> created at line 375.
Found 8-bit 8-to-1 multiplexer for signal <counter_row[2]_GND_19_o_wide_mux_206_OUT> created at line 326.
Found 1-bit 64-to-1 multiplexer for signal <counter_row[2]_board_state[63][3]_wide_mux_202_OUT<3>> created at line 0.
Found 1-bit 64-to-1 multiplexer for signal <counter_row[2]_board_state[63][3]_wide_mux_168_OUT<2>> created at line 326.
Found 1-bit 64-to-1 multiplexer for signal <counter_row[2]_board_state[63][3]_wide_mux_168_OUT<1>> created at line 326.
Found 1-bit 64-to-1 multiplexer for signal <counter_row[2]_board_state[63][3]_wide_mux_168_OUT<0>> created at line 326.
Found 10-bit comparator lessequal for signal <n0067> created at line 179
Found 10-bit comparator lessequal for signal <n0070> created at line 182
Found 10-bit comparator lessequal for signal <n0073> created at line 185
Found 10-bit comparator lessequal for signal <n0076> created at line 188
Found 10-bit comparator lessequal for signal <n0079> created at line 191
Found 10-bit comparator lessequal for signal <n0082> created at line 194
Found 10-bit comparator lessequal for signal <n0085> created at line 197
Found 10-bit comparator lessequal for signal <n0103> created at line 211
Found 10-bit comparator lessequal for signal <n0106> created at line 214
Found 10-bit comparator lessequal for signal <n0109> created at line 217
Found 10-bit comparator lessequal for signal <n0112> created at line 220
Found 10-bit comparator lessequal for signal <n0115> created at line 223
Found 10-bit comparator lessequal for signal <n0118> created at line 226
Found 10-bit comparator lessequal for signal <n0121> created at line 229
Found 7-bit comparator lessequal for signal <n0139> created at line 241
Found 7-bit comparator lessequal for signal <n0141> created at line 243
Found 7-bit comparator lessequal for signal <n0143> created at line 245
Found 7-bit comparator lessequal for signal <n0145> created at line 247
Found 7-bit comparator lessequal for signal <n0147> created at line 249
Found 7-bit comparator lessequal for signal <n0149> created at line 251
Found 7-bit comparator lessequal for signal <n0151> created at line 253
Found 7-bit comparator lessequal for signal <n0160> created at line 263
Found 7-bit comparator lessequal for signal <n0162> created at line 265
Found 7-bit comparator lessequal for signal <n0164> created at line 267
Found 7-bit comparator lessequal for signal <n0166> created at line 269
Found 7-bit comparator lessequal for signal <n0168> created at line 271
Found 7-bit comparator lessequal for signal <n0170> created at line 273
Found 7-bit comparator lessequal for signal <n0172> created at line 275
Found 7-bit comparator lessequal for signal <n0181> created at line 283
Found 7-bit comparator lessequal for signal <n0183> created at line 283
Found 7-bit comparator lessequal for signal <n0186> created at line 284
Found 7-bit comparator lessequal for signal <n0189> created at line 284
Found 10-bit comparator lessequal for signal <n0192> created at line 286
Found 10-bit comparator greater for signal <CounterX[9]_PWR_15_o_LessThan_161_o> created at line 286
Found 10-bit comparator lessequal for signal <n0195> created at line 287
Found 10-bit comparator greater for signal <CounterY[9]_GND_19_o_LessThan_163_o> created at line 287
Found 6-bit comparator equal for signal <CURSOR_ADDR[5]_counter_row[2]_equal_164_o> created at line 301
Found 6-bit comparator equal for signal <SELECT_ADDR[5]_counter_row[2]_equal_165_o> created at line 303
Summary:
inferred 2 Adder/Subtractor(s).
inferred 8 D-type flip-flop(s).
inferred 38 Comparator(s).
inferred 115 Multiplexer(s).
Unit <chess_display_controller> synthesized.
Synthesizing Unit <VGAsync_controller>.
Related source file is "/home/ise/Shared/VHDL_CHESS_Project/VGAsync_controller.vhd".
Found 10-bit register for signal <CounterY_int>.
Found 1-bit register for signal <vga_HS>.
Found 1-bit register for signal <vga_VS>.
Found 1-bit register for signal <inDisplayArea_int>.
Found 10-bit register for signal <CounterX_int>.
Found 10-bit adder for signal <CounterX_int[9]_GND_20_o_add_3_OUT> created at line 1241.
Found 10-bit adder for signal <CounterY_int[9]_GND_20_o_add_9_OUT> created at line 1241.
Found 10-bit comparator greater for signal <PWR_16_o_CounterX_int[9]_LessThan_15_o> created at line 77
Found 10-bit comparator greater for signal <CounterX_int[9]_PWR_16_o_LessThan_16_o> created at line 77
Found 10-bit comparator greater for signal <CounterX_int[9]_PWR_16_o_LessThan_19_o> created at line 99
Found 10-bit comparator greater for signal <CounterY_int[9]_GND_20_o_LessThan_20_o> created at line 99
Summary:
inferred 2 Adder/Subtractor(s).
inferred 23 D-type flip-flop(s).
inferred 4 Comparator(s).
inferred 2 Multiplexer(s).
Unit <VGAsync_controller> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 1
64x4-bit single-port Read Only RAM : 1
# Adders/Subtractors : 124
10-bit adder : 2
14-bit adder : 4
27-bit adder : 1
3-bit adder : 1
3-bit subtractor : 5
6-bit adder : 9
6-bit addsub : 1
6-bit subtractor : 35
7-bit adder : 42
7-bit subtractor : 16
8-bit adder : 8
# Registers : 25
1-bit register : 11
10-bit register : 2
14-bit register : 4
2-bit register : 1
256-bit register : 1
27-bit register : 1
4-bit register : 1
6-bit register : 3
8-bit register : 1
# Comparators : 86
10-bit comparator greater : 6
10-bit comparator lessequal : 16
3-bit comparator equal : 2
3-bit comparator greater : 3
3-bit comparator lessequal : 2
4-bit comparator equal : 3
4-bit comparator greater : 2
4-bit comparator lessequal : 28
6-bit comparator equal : 6
7-bit comparator lessequal : 18
# Multiplexers : 776
1-bit 2-to-1 multiplexer : 575
1-bit 64-to-1 multiplexer : 4
1-bit 8-to-1 multiplexer : 2
10-bit 2-to-1 multiplexer : 2
14-bit 2-to-1 multiplexer : 24
2-bit 2-to-1 multiplexer : 3
3-bit 2-to-1 multiplexer : 14
4-bit 2-to-1 multiplexer : 6
4-bit 64-to-1 multiplexer : 107
6-bit 2-to-1 multiplexer : 15
7-bit 2-to-1 multiplexer : 14
8-bit 2-to-1 multiplexer : 9
8-bit 8-to-1 multiplexer : 1
# FSMs : 5
# Xors : 3
1-bit xor2 : 3
=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <VGAsync_controller>.
The following registers are absorbed into counter <CounterX_int>: 1 register on signal <CounterX_int>.
The following registers are absorbed into counter <CounterY_int>: 1 register on signal <CounterY_int>.
Unit <VGAsync_controller> synthesized (advanced).
Synthesizing (advanced) Unit <chess_logic_module>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_board_out_addr[5]_GND_10_o_wide_mux_81_OUT> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 64-word x 4-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <board_out_addr> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <chess_logic_module> synthesized (advanced).
Synthesizing (advanced) Unit <chess_module>.
The following registers are absorbed into counter <DIV_CLK>: 1 register on signal <DIV_CLK>.
Unit <chess_module> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
64x4-bit single-port distributed Read Only RAM : 1
# Adders/Subtractors : 121
14-bit adder : 4
3-bit adder : 1
3-bit subtractor : 5
6-bit adder : 58
6-bit addsub : 1
6-bit subtractor : 49
7-bit subtractor : 2
8-bit adder : 1
# Counters : 3
10-bit up counter : 2
27-bit up counter : 1
# Registers : 355
Flip-Flops : 355
# Comparators : 86
10-bit comparator greater : 6
10-bit comparator lessequal : 16
3-bit comparator equal : 2
3-bit comparator greater : 3
3-bit comparator lessequal : 2
4-bit comparator equal : 3
4-bit comparator greater : 2
4-bit comparator lessequal : 28
6-bit comparator equal : 6
7-bit comparator lessequal : 18
# Multiplexers : 774
1-bit 2-to-1 multiplexer : 575
1-bit 64-to-1 multiplexer : 4
1-bit 8-to-1 multiplexer : 2
14-bit 2-to-1 multiplexer : 24
2-bit 2-to-1 multiplexer : 3
3-bit 2-to-1 multiplexer : 14
4-bit 2-to-1 multiplexer : 6
4-bit 64-to-1 multiplexer : 107
6-bit 2-to-1 multiplexer : 15
7-bit 2-to-1 multiplexer : 14
8-bit 2-to-1 multiplexer : 9
8-bit 8-to-1 multiplexer : 1
# FSMs : 5
# Xors : 3
1-bit xor2 : 3
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <L_debounce_inst/FSM_0> on signal <state[1:3]> with user encoding.
Optimizing FSM <U_debounce_inst/FSM_0> on signal <state[1:3]> with user encoding.
Optimizing FSM <D_debounce_inst/FSM_0> on signal <state[1:3]> with user encoding.
Optimizing FSM <R_debounce_inst/FSM_0> on signal <state[1:3]> with user encoding.
---------------------
State | Encoding
---------------------
init | 000
wq | 001
scen_st | 010
ccr | 011
wfcr | 100
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <logic_module/FSM_1> on signal <current_state[1:3]> with user encoding.
-------------------
State | Encoding
-------------------
000 | 000
010 | 010
001 | 001
011 | 011
100 | 100
101 | 101
110 | 110
111 | 111
-------------------
WARNING:Xst:2677 - Node <DIV_CLK_12> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_13> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_14> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_15> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_16> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_17> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_18> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_19> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_20> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_21> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_22> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_23> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_24> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_25> of sequential type is unconnected in block <chess_module>.
WARNING:Xst:2677 - Node <DIV_CLK_26> of sequential type is unconnected in block <chess_module>.
Optimizing unit <chess_module> ...
Optimizing unit <button_debounce> ...
Optimizing unit <chess_logic_module> ...
Optimizing unit <path_check> ...
Optimizing unit <chess_display_controller> ...
INFO:Xst:2261 - The FF/Latch <output_color_3> in Unit <chess_display_controller> is equivalent to the following FF/Latch, which will be removed : <output_color_4>
Optimizing unit <VGAsync_controller> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block chess_module, actual ratio is 34.
FlipFlop logic_module/selected_addr_internal_0 has been replicated 1 time(s)
FlipFlop logic_module/selected_addr_internal_1 has been replicated 1 time(s)
FlipFlop logic_module/selected_addr_internal_2 has been replicated 1 time(s)
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 404
Flip-Flops : 404
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : chess_module.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1912
# GND : 1
# INV : 7
# LUT1 : 63
# LUT2 : 50
# LUT3 : 97
# LUT4 : 109
# LUT5 : 454
# LUT6 : 905
# MUXCY : 91
# MUXF7 : 34
# VCC : 1
# XORCY : 100
# FlipFlops/Latches : 404
# FD : 1
# FDC : 99
# FDCE : 263
# FDE : 9
# FDP : 3
# FDR : 19
# FDRE : 10
# Clock Buffers : 6
# BUFG : 6
# IO Buffers : 26
# IBUF : 8
# IBUFG : 1
# OBUF : 17
# DCMs : 1
# DCM_SP : 1
Device utilization summary:
---------------------------
Selected Device : 6slx9tqg144-3
Slice Logic Utilization:
Number of Slice Registers: 404 out of 11440 3%
Number of Slice LUTs: 1685 out of 5720 29%
Number used as Logic: 1685 out of 5720 29%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1963
Number with an unused Flip Flop: 1559 out of 1963 79%
Number with an unused LUT: 278 out of 1963 14%
Number of fully used LUT-FF pairs: 126 out of 1963 6%
Number of unique control sets: 16
IO Utilization:
Number of IOs: 26
Number of bonded IOBs: 26 out of 102 25%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 6 out of 16 37%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
DIV_CLK_11 | BUFG | 362 |
ClkPort | DCM_SP:CLKFX+BUFG | 12 |
DIV_CLK_1 | BUFG | 30 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 13.279ns (Maximum Frequency: 75.306MHz)
Minimum input arrival time before clock: 4.515ns
Maximum output required time after clock: 15.528ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'DIV_CLK_11'
Clock period: 13.279ns (frequency: 75.306MHz)
Total number of paths / destination ports: 2199296 / 633
-------------------------------------------------------------------------
Delay: 13.279ns (Levels of Logic = 11)
Source: logic_module/selected_addr_internal_1 (FF)
Destination: logic_module/board_out_piece_1 (FF)
Source Clock: DIV_CLK_11 rising
Destination Clock: DIV_CLK_11 rising
Data Path: logic_module/selected_addr_internal_1 to logic_module/board_out_piece_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 228 0.447 2.061 logic_module/selected_addr_internal_1 (logic_module/selected_addr_internal_1)
LUT2:I1->O 28 0.205 1.235 logic_module/path_checker/n1441<2>1 (logic_module/path_checker/n1441<2>)
LUT6:I5->O 2 0.205 0.845 logic_module/path_checker/GND_17_o_GND_17_o_sub_520_OUT<5>_8 (logic_module/path_checker/GND_17_o_GND_17_o_sub_520_OUT<5>_8)
LUT3:I0->O 1 0.205 0.580 logic_module/path_checker/h_delta[3]_GND_17_o_OR_164_o3 (logic_module/path_checker/h_delta[3]_GND_17_o_OR_164_o3)
LUT5:I4->O 3 0.205 0.879 logic_module/path_checker/h_delta[3]_GND_17_o_OR_164_o4 (logic_module/path_checker/h_delta[3]_GND_17_o_OR_164_o4)
LUT6:I3->O 3 0.205 0.651 logic_module/path_checker/h_delta[3]_GND_17_o_OR_164_o5 (logic_module/path_checker/h_delta[3]_GND_17_o_OR_164_o)
LUT6:I5->O 2 0.205 0.617 logic_module/path_checker/h_delta[3]_GND_17_o_OR_168_o5 (logic_module/path_checker/h_delta[3]_GND_17_o_OR_168_o)
LUT6:I5->O 1 0.205 0.684 logic_module/path_checker/h_delta[3]_GND_17_o_OR_172_o5 (logic_module/path_checker/h_delta[3]_GND_17_o_OR_172_o)
LUT6:I4->O 2 0.203 0.617 logic_module/Mmux_move_legal17222 (logic_module/Mmux_move_legal17222)
LUT6:I5->O 1 0.205 0.580 logic_module/Mmux_move_legal166_SW0_SW0 (N238)
LUT6:I5->O 3 0.205 0.651 logic_module/Mmux_move_legal166 (logic_module/Mmux_move_legal173)
LUT6:I5->O 10 0.205 0.856 logic_module/_n0646_inv1_cepot (logic_module/_n0631_inv_cepot)