Added syscfg enabling to RCC, required fo rinterrupts

David-OConnor · Apr 3, 2021 · f713979 · f713979
1 parent e1cc12b
commit f713979
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Showing 5 changed files with 30 additions and 11 deletions.
diff --git a/src/clocks/f.rs b/src/clocks/f.rs
@@ -438,6 +438,12 @@ impl Clocks {
 
         rcc.cr.modify(|_, w| w.csson().bit(self.security_system));
 
+        // Enable and reset System Configuration Controller, ie for interrupts.
+        // todo: Is this the right module to do this in?
+        rcc.apb2enr.modify(|_, w| w.syscfgen().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.syscfgrst().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.syscfgrst().clear_bit());
+
         Ok(())
     }
 

diff --git a/src/clocks/h7.rs b/src/clocks/h7.rs
@@ -349,6 +349,13 @@ impl Clocks {
         //     while rcc.crrcr.read().hsi48rdy().bit_is_clear() {}
         // }
 
+        // Enable and reset System Configuration Controller, ie for interrupts.
+        // todo: Is this the right module to do this in?
+        rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
+        rcc.apb4rstr.modify(|_, w| w.syscfgrst().set_bit());
+        rcc.apb4rstr.modify(|_, w| w.syscfgrst().clear_bit());
+
+
         Ok(())
     }
 

diff --git a/src/clocks/l_g.rs b/src/clocks/l_g.rs
@@ -702,6 +702,20 @@ impl Clocks {
             while rcc.crrcr.read().hsi48rdy().bit_is_clear() {}
         }
 
+        // Enable and reset System Configuration Controller, ie for interrupts.
+        // todo: Is this the right module to do this in?
+        cfg_if! {
+            if #[cfg(any(feature = "l4", feature = "l5", feature = "g4"))] {
+                rcc.apb2enr.modify(|_, w| w.syscfgen().set_bit());
+                rcc.apb2rstr.modify(|_, w| w.syscfgrst().set_bit());
+                rcc.apb2rstr.modify(|_, w| w.syscfgrst().clear_bit());
+            } else {  // G0
+                rcc.apbenr2.modify(|_, w| w.syscfgen().set_bit());
+                rcc.apbrstr2.modify(|_, w| w.syscfgrst().set_bit());
+                rcc.apbrstr2.modify(|_, w| w.syscfgrst().clear_bit());
+            }
+        }
+
         Ok(())
     }
 

diff --git a/src/gpio.rs b/src/gpio.rs
@@ -241,8 +241,6 @@ macro_rules! make_port {
                     let mut result = [<Gpio $Port Pin>] {
                         port: PortLetter::[<$Port>],
                         pin,
-                        // mode,
-                        // output_type: OutputType::PushPull, // Registers initialize to this.
                     };
                     result.mode(mode, &mut self.regs);
 
@@ -410,8 +408,6 @@ macro_rules! make_pin {
             pub fn mode(&mut self, value: PinMode, regs: &mut pac::[<GPIO $Port>]) {
                 set_field!(self.pin, regs, moder, moder, bits, value.val(), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
 
-                // self.mode = value;
-
                 if let PinMode::Alt(alt) = value {
                     self.alt_fn(alt, regs);
                 }
@@ -420,8 +416,6 @@ macro_rules! make_pin {
             /// Set output type.
             pub fn output_type(&mut self, value: OutputType, regs: &mut pac::[<GPIO $Port>]) {
                 set_field!(self.pin, regs, otyper, ot, bit, value as u8 != 0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
-
-                // self.output_type = value;
             }
 
             /// Set output speed.

diff --git a/src/rtc.rs b/src/rtc.rs
@@ -150,7 +150,6 @@ impl Rtc {
         // Enable the peripheral clock for communication
         // You must enable the `pwren()` bit before making RTC register writes, or they won't stay
         // set. Enable the backup interface by setting PWREN
-        // Unlock the backup domain
 
         // Note that unlock other RCC enableing processes, there's no corresponding reset
         // field here.
@@ -166,14 +165,14 @@ impl Rtc {
                 rcc.apb1enr1.modify(|_, w| w.pwren().set_bit());
                 rcc.apb1enr1.modify(|_, w| w.rtcapben().set_bit());
                 rcc.apb1smenr1.modify(|_, w| w.rtcapbsmen().set_bit());  // In sleep and stop modes.
-                pwr.cr1.read(); // read to allow the pwr clock to enable
-                pwr.cr1.modify( | _, w| w.dbp().set_bit());
+                pwr.cr1.read(); // Read to allow the pwr clock to enable
+                pwr.cr1.modify( | _, w| w.dbp().set_bit()); // Unlock the backup domain
                 while pwr.cr1.read().dbp().bit_is_clear() {}
             } else if #[cfg(any(feature = "g0"))] {
                 rcc.apbenr1.modify(|_, w| w.pwren().set_bit());
                 rcc.apbenr1.modify(|_, w| w.rtcapben().set_bit());
                 rcc.apbsmenr1.modify(|_, w| w.rtcapbsmen().set_bit());  // In sleep and stop modes.
-                pwr.cr1.read(); // read to allow the pwr clock to enable
+                pwr.cr1.read();
                 pwr.cr1.modify( | _, w| w.dbp().set_bit());
                 while pwr.cr1.read().dbp().bit_is_clear() {}
             } else { // eg h7
@@ -183,7 +182,6 @@ impl Rtc {
                 pwr.cr1.modify( | _, w| w.dbp().set_bit());
                 while pwr.cr1.read().dbp().bit_is_clear() {}
             }
-
         }
 
         // Reset the backup domain.