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vivado_3716.backup.log
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vivado_3716.backup.log
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#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon Mar 29 18:46:54 2021
# Process ID: 3716
# Current directory: F:/Lab 9-10
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent26112 F:\Lab 9-10\Lab 9-10.xpr
# Log file: F:/Lab 9-10/vivado.log
# Journal file: F:/Lab 9-10\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {F:/Lab 9-10/Lab 9-10.xpr}
INFO: [Project 1-313] Project file moved from 'C:/Users/daksh/Documents/Academic/Semester 2/Practicals/Computer Architecture/Lab 01/Lab 9-10' since last save.
CRITICAL WARNING: [Project 1-311] Could not find the file 'F:/Lab 3/Lab 3.srcs/sources_1/new/FA.vhd', nor could it be found using path 'C:/Users/daksh/Documents/Academic/Semester 2/Practicals/Computer Architecture/Lab 01/Lab 3/Lab 3.srcs/sources_1/new/FA.vhd'.
CRITICAL WARNING: [Project 1-311] Could not find the file 'F:/Lab 3/Lab 3.srcs/sources_1/new/HA.vhd', nor could it be found using path 'C:/Users/daksh/Documents/Academic/Semester 2/Practicals/Computer Architecture/Lab 01/Lab 3/Lab 3.srcs/sources_1/new/HA.vhd'.
CRITICAL WARNING: [Project 1-311] Could not find the file 'F:/Lab 5/Lab 5.srcs/sources_1/new/D_FF.vhd', nor could it be found using path 'C:/Users/daksh/Documents/Academic/Semester 2/Practicals/Computer Architecture/Lab 01/Lab 5/Lab 5.srcs/sources_1/new/D_FF.vhd'.
CRITICAL WARNING: [Project 1-311] Could not find the file 'F:/Lab 5/Lab 5.srcs/sources_1/new/Slow_clk.vhd', nor could it be found using path 'C:/Users/daksh/Documents/Academic/Semester 2/Practicals/Computer Architecture/Lab 01/Lab 5/Lab 5.srcs/sources_1/new/Slow_clk.vhd'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.
open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 837.023 ; gain = 64.535
update_compile_order -fileset sources_1
set_property top MUX_8_to_1_Sim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
set_property top MUX_8_to_1 [current_fileset]
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'MUX_8_to_1_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj MUX_8_to_1_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/new/MUX_8_to_1.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity MUX_8_to_1
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/new/tri_state_buffer_4bit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tri_state_buffer_4bit
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/MUX_8_to_1_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity MUX_8_to_1_Sim
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot MUX_8_to_1_Sim_behav xil_defaultlib.MUX_8_to_1_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default]
Compiling architecture behavioral of entity xil_defaultlib.tri_state_buffer_4bit [tri_state_buffer_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.MUX_8_to_1 [mux_8_to_1_default]
Compiling architecture behavioral of entity xil_defaultlib.mux_8_to_1_sim
Built simulation snapshot MUX_8_to_1_Sim_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source F:/Lab -notrace
couldn't read file "F:/Lab": no such file or directory
INFO: [Common 17-206] Exiting Webtalk at Mon Mar 29 18:54:29 2021...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 868.047 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "MUX_8_to_1_Sim_behav -key {Behavioral:sim_1:Functional:MUX_8_to_1_Sim} -tclbatch {MUX_8_to_1_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source MUX_8_to_1_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'MUX_8_to_1_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 871.285 ; gain = 3.238
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Mux_2way_4bit_sim.vhd} w ]
add_files -fileset sim_1 {{F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Mux_2way_4bit_sim.vhd}}
update_compile_order -fileset sim_1
set_property top Mux_2way_4bit_sim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Mux_2way_4bit_sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Mux_2way_4bit_sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/new/MUX_2way_4bit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity MUX_2way_4bit
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Mux_2way_4bit_sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Mux_2way_4bit_sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Mux_2way_4bit_sim_behav xil_defaultlib.Mux_2way_4bit_sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.tri_state_buffer_4bit [tri_state_buffer_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.MUX_2way_4bit [mux_2way_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.mux_2way_4bit_sim
Built simulation snapshot Mux_2way_4bit_sim_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source F:/Lab -notrace
couldn't read file "F:/Lab": no such file or directory
INFO: [Common 17-206] Exiting Webtalk at Mon Mar 29 19:02:27 2021...
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Mux_2way_4bit_sim_behav -key {Behavioral:sim_1:Functional:Mux_2way_4bit_sim} -tclbatch {Mux_2way_4bit_sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Mux_2way_4bit_sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Mux_2way_4bit_sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 910.406 ; gain = 7.848
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Mux_2way_3bit_sim.vhd} w ]
add_files -fileset sim_1 {{F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Mux_2way_3bit_sim.vhd}}
update_compile_order -fileset sim_1
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Mux_2way_4bit_sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Mux_2way_4bit_sim_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Mux_2way_4bit_sim_behav xil_defaultlib.Mux_2way_4bit_sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Mux_2way_4bit_sim_behav -key {Behavioral:sim_1:Functional:Mux_2way_4bit_sim} -tclbatch {Mux_2way_4bit_sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Mux_2way_4bit_sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Mux_2way_4bit_sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 916.668 ; gain = 1.742
import_files -norecurse {{D:/Viavdo Projects/src/D_FF.vhd}}
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd} w ]
add_files -fileset sim_1 {{F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd}}
update_compile_order -fileset sim_1
set_property top Program_Counter_Sim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Program_Counter_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Program_Counter_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/D_FF.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity D_FF
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/new/Program_Counter.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_Counter
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_Counter_Sim
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Program_Counter_Sim_behav xil_defaultlib.Program_Counter_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.D_FF [d_ff_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_Counter [program_counter_default]
Compiling architecture behavioral of entity xil_defaultlib.program_counter_sim
Built simulation snapshot Program_Counter_Sim_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source F:/Lab -notrace
couldn't read file "F:/Lab": no such file or directory
INFO: [Common 17-206] Exiting Webtalk at Mon Mar 29 19:20:57 2021...
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Program_Counter_Sim_behav -key {Behavioral:sim_1:Functional:Program_Counter_Sim} -tclbatch {Program_Counter_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Program_Counter_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Program_Counter_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 935.387 ; gain = 6.488
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Program_Counter_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Program_Counter_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_Counter_Sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Program_Counter_Sim_behav xil_defaultlib.Program_Counter_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.D_FF [d_ff_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_Counter [program_counter_default]
Compiling architecture behavioral of entity xil_defaultlib.program_counter_sim
Built simulation snapshot Program_Counter_Sim_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Program_Counter_Sim_behav -key {Behavioral:sim_1:Functional:Program_Counter_Sim} -tclbatch {Program_Counter_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Program_Counter_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Program_Counter_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 938.000 ; gain = 0.469
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Program_Counter_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Program_Counter_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_Counter_Sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Program_Counter_Sim_behav xil_defaultlib.Program_Counter_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.D_FF [d_ff_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_Counter [program_counter_default]
Compiling architecture behavioral of entity xil_defaultlib.program_counter_sim
Built simulation snapshot Program_Counter_Sim_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Program_Counter_Sim_behav -key {Behavioral:sim_1:Functional:Program_Counter_Sim} -tclbatch {Program_Counter_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Program_Counter_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Program_Counter_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 939.223 ; gain = 0.730
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Program_Counter_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Program_Counter_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_Counter_Sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Program_Counter_Sim_behav xil_defaultlib.Program_Counter_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.D_FF [d_ff_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_Counter [program_counter_default]
Compiling architecture behavioral of entity xil_defaultlib.program_counter_sim
Built simulation snapshot Program_Counter_Sim_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Program_Counter_Sim_behav -key {Behavioral:sim_1:Functional:Program_Counter_Sim} -tclbatch {Program_Counter_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Program_Counter_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Program_Counter_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 943.047 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Program_Counter_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Program_Counter_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_Counter_Sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Program_Counter_Sim_behav xil_defaultlib.Program_Counter_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.D_FF [d_ff_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_Counter [program_counter_default]
Compiling architecture behavioral of entity xil_defaultlib.program_counter_sim
Built simulation snapshot Program_Counter_Sim_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Program_Counter_Sim_behav -key {Behavioral:sim_1:Functional:Program_Counter_Sim} -tclbatch {Program_Counter_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Program_Counter_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Program_Counter_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 943.047 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Program_Counter_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Program_Counter_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Program_Counter_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_Counter_Sim
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Program_Counter_Sim_behav xil_defaultlib.Program_Counter_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.D_FF [d_ff_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_Counter [program_counter_default]
Compiling architecture behavioral of entity xil_defaultlib.program_counter_sim
Built simulation snapshot Program_Counter_Sim_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Program_Counter_Sim_behav -key {Behavioral:sim_1:Functional:Program_Counter_Sim} -tclbatch {Program_Counter_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Program_Counter_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Program_Counter_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 945.094 ; gain = 0.000
import_files -norecurse {{D:/Viavdo Projects/src/FA.vhd} {D:/Viavdo Projects/src/Slow_Clk.vhd} {D:/Viavdo Projects/src/HA.vhd}}
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/TBA_Sim.vhd} w ]
add_files -fileset sim_1 {{F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/TBA_Sim.vhd}}
update_compile_order -fileset sim_1
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Program_Counter_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Program_Counter_Sim_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Program_Counter_Sim_behav xil_defaultlib.Program_Counter_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Program_Counter_Sim_behav -key {Behavioral:sim_1:Functional:Program_Counter_Sim} -tclbatch {Program_Counter_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Program_Counter_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Program_Counter_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 948.734 ; gain = 0.000
set_property top TBA_Sim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'TBA_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj TBA_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/FA.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity FA
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/HA.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity HA
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/new/TBA.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity TBA
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/TBA_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity TBA_Sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TBA_Sim_behav xil_defaultlib.TBA_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default]
Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default]
Compiling architecture behavioral of entity xil_defaultlib.TBA [tba_default]
Compiling architecture behavioral of entity xil_defaultlib.tba_sim
Built simulation snapshot TBA_Sim_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source F:/Lab -notrace
couldn't read file "F:/Lab": no such file or directory
INFO: [Common 17-206] Exiting Webtalk at Mon Mar 29 19:46:34 2021...
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "TBA_Sim_behav -key {Behavioral:sim_1:Functional:TBA_Sim} -tclbatch {TBA_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source TBA_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'TBA_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 949.523 ; gain = 0.789
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'TBA_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj TBA_Sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/TBA_Sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity TBA_Sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TBA_Sim_behav xil_defaultlib.TBA_Sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default]
Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default]
Compiling architecture behavioral of entity xil_defaultlib.TBA [tba_default]
Compiling architecture behavioral of entity xil_defaultlib.tba_sim
Built simulation snapshot TBA_Sim_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "TBA_Sim_behav -key {Behavioral:sim_1:Functional:TBA_Sim} -tclbatch {TBA_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source TBA_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'TBA_Sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 956.527 ; gain = 0.000
import_files -norecurse {{D:/Viavdo Projects/src/tri_state_buffer.vhd}}
update_compile_order -fileset sources_1
export_ip_user_files -of_objects [get_files {{F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/tri_state_buffer.vhd}}] -no_script -reset -force -quiet
remove_files {{F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/tri_state_buffer.vhd}}
file delete -force {F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/tri_state_buffer.vhd}
import_files -norecurse {{D:/Viavdo Projects/src/Reg_bank.vhd}}
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Reg_bank_sim.vhd} w ]
add_files -fileset sim_1 {{F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Reg_bank_sim.vhd}}
update_compile_order -fileset sim_1
set_property top Reg_bank_sim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Reg_bank_sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Reg_bank_sim_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Reg_bank
INFO: [VRFC 10-163] Analyzing VHDL file "F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Reg_bank_sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Reg_bank_sim
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Reg_bank_sim_behav xil_defaultlib.Reg_bank_sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:46]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:53]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:60]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:67]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:74]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:81]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:88]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:95]
ERROR: [VRFC 10-664] expression has 3 elements ; expected 4 [F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Reg_bank_sim.vhd:63]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit reg_bank_sim in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 972.148 ; gain = 5.652
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Reg_bank_sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Reg_bank_sim_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 52dcb91c77fa4d91b387034ee4c96723 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Reg_bank_sim_behav xil_defaultlib.Reg_bank_sim -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:46]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:53]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:60]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:67]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:74]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:81]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:88]
WARNING: [VRFC 10-122] reg remains a black-box since it has no binding entity [F:/Lab 9-10/Lab 9-10.srcs/sources_1/imports/src/Reg_bank.vhd:95]
ERROR: [VRFC 10-664] expression has 3 elements ; expected 4 [F:/Lab 9-10/Lab 9-10.srcs/sim_1/new/Reg_bank_sim.vhd:63]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit reg_bank_sim in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'F:/Lab 9-10/Lab 9-10.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
close_sim
INFO: [Simtcl 6-16] Simulation closed
current_sim simulation_10
close_sim
INFO: [Simtcl 6-16] Simulation closed
current_sim simulation_3
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Mon Mar 29 19:59:15 2021...