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Simulate.cpp
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Simulate.cpp
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#include "Simulate.h"
// memory
unsigned char memory[MEM_SIZE] = {0};
// regisiter set
REG reg[32] = {0};
// PC
ULL PC = 0;
ULL endPC = 0;
int exit_flag = 0;
bool Mispredicted = false;
int ALUWait = 0;
bool wait_finish_flag = false;
int btbReplaceIdx = 0;
// instruction string
char InstBuf[100] = "";
int InstCount = 0;
int CycleCount = 0;
float CPI = 0.0f;
int DataHazardCount = 0;
int LoadUseHazardCount = 0;
int BypassCount = 0;
int MispredictedCount = 0;
int PredictableCount = 0;
int PredictCorrectCount = 0;
float PredictiveAccuracy = 0.0f;
// transmission
STAGEMODE StageMode[5], StageModeOld[5];
BTB btb[BTB_SIZE];
IFID IF_ID, IF_ID_old;
IDEX ID_EX, ID_EX_old;
EXMEM EX_MEM, EX_MEM_old;
MEMWB MEM_WB, MEM_WB_old;
void setup()
{
memset(InstBuf, 0, sizeof(InstBuf));
Mispredicted = false;
exit_flag = 0;
ALUWait = 0;
wait_finish_flag = false;
btbReplaceIdx = 0;
for (int i = 0; i < BTB_SIZE; ++i)
{
btb[i].valid = false;
}
StageMode[STAGE_IF] = MODE_LOAD;
StageMode[STAGE_ID] = MODE_BUBBLE;
StageMode[STAGE_EX] = MODE_BUBBLE;
StageMode[STAGE_MEM] = MODE_BUBBLE;
StageMode[STAGE_WB] = MODE_BUBBLE;
for (int i = 0; i < 5; ++i)
StageModeOld[i] = MODE_BUBBLE;
for (int i = 0; i < 32; ++i)
reg[i] = 0;
memset(memory, 0, MEM_SIZE);
load_memory();
PC = mainAddr;
endPC = ((mainAddr + mainSize - 3) / 16) * 16;
reg[R_gp] = gp;
reg[R_sp] = P_TO_V(MEM_ED);
InstCount = 0;
CycleCount = 0;
CPI = 0.0f;
DataHazardCount = 0;
LoadUseHazardCount = 0;
BypassCount = 0;
MispredictedCount = 0;
PredictableCount = 0;
PredictCorrectCount = 0;
PredictiveAccuracy = 0.0f;
}
// load code and data
void load_memory()
{
memset(memory, 0, sizeof(char) * MEM_SIZE);
fseek(file, cOffset, SEEK_SET);
fread(&memory[V_TO_P(cVadr)], 1, cSize, file);
fseek(file, dOffset, SEEK_SET);
fread(&memory[V_TO_P(dVadr)], 1, dSize, file);
}
bool simulate_one_step()
{
if (ALUWait == 0 && PC == endPC)
{
StageMode[STAGE_IF] = MODE_BUBBLE;
bool exit_this_cycle = true;
for (int i = 1; i < 5; ++i)
if (StageMode[i] != MODE_BUBBLE)
{
exit_this_cycle = false;
break;
}
if (exit_this_cycle)
return false;
}
reg[0] = 0; // register zero should alwarys be 0
Mispredicted = false;
wait_finish_flag = (ALUWait == 1) ? true : false;
// set stall
if (ALUWait > 0) // wait for division
{
StageMode[STAGE_IF] = MODE_STALL;
StageMode[STAGE_ID] = MODE_STALL;
StageMode[STAGE_EX] = MODE_STALL;
}
#ifdef BYPASS
if (StageMode[STAGE_ID] != MODE_BUBBLE && StageMode[STAGE_EX] == MODE_LOAD &&
((IF_ID_old.RegRs1 != R_zero && IF_ID_old.RegRs1 == ID_EX_old.RegDst &&
ID_EX_old.Ctrl_WB_RegWrite == REGWRITE_VALM) ||
(IF_ID_old.RegRs2 != R_zero && IF_ID_old.RegRs2 == ID_EX_old.RegDst &&
ID_EX_old.Ctrl_WB_RegWrite == REGWRITE_VALM)))
{
StageMode[STAGE_IF] = MODE_STALL;
StageMode[STAGE_ID] = MODE_STALL;
}
#else
if (StageMode[STAGE_ID] != MODE_BUBBLE &&
((IF_ID_old.RegRs1 != R_zero &&
((StageMode[STAGE_EX] == MODE_LOAD && IF_ID_old.RegRs1 == ID_EX_old.RegDst) ||
(StageMode[STAGE_MEM] == MODE_LOAD && IF_ID_old.RegRs1 == EX_MEM_old.RegDst) ||
(StageMode[STAGE_WB] == MODE_LOAD && IF_ID_old.RegRs1 == MEM_WB_old.RegDst))) ||
(IF_ID_old.RegRs2 != R_zero &&
((StageMode[STAGE_EX] == MODE_LOAD && IF_ID_old.RegRs2 == ID_EX_old.RegDst) ||
(StageMode[STAGE_MEM] == MODE_LOAD && IF_ID_old.RegRs2 == EX_MEM_old.RegDst) ||
(StageMode[STAGE_WB] == MODE_LOAD &&
IF_ID_old.RegRs2 == MEM_WB_old.RegDst))))) // data hazard
{
StageMode[STAGE_IF] = MODE_STALL;
StageMode[STAGE_ID] = MODE_STALL;
if (StageMode[STAGE_EX] == MODE_LOAD &&
((IF_ID_old.RegRs1 != R_zero && IF_ID_old.RegRs1 == ID_EX_old.RegDst &&
ID_EX_old.Ctrl_WB_RegWrite == REGWRITE_VALM) ||
(IF_ID_old.RegRs2 != R_zero && IF_ID_old.RegRs2 == ID_EX_old.RegDst &&
ID_EX_old.Ctrl_WB_RegWrite == REGWRITE_VALM)))
LoadUseHazardCount++;
else
DataHazardCount++;
}
#endif
// update ALUWait
if (ALUWait > 0)
ALUWait--;
// run
IF();
ID();
EX();
MEM();
WB();
// update bubble
for (int i = 0; i < 5; ++i)
{
StageModeOld[i] = StageMode[i];
StageMode[i] = MODE_LOAD;
}
for (int i = 0; i < 4; ++i) // pass bubble
{
if (StageModeOld[i] == MODE_BUBBLE)
{
StageMode[i + 1] = MODE_BUBBLE;
}
}
// set bubble
#ifdef BYPASS
if (StageModeOld[STAGE_ID] != MODE_BUBBLE)
{
if (IF_ID_old.RegRs1 != R_zero)
{
if ((StageModeOld[STAGE_EX] == MODE_LOAD || wait_finish_flag) &&
IF_ID_old.RegRs1 == ID_EX_old.RegDst)
{
switch (ID_EX_old.Ctrl_WB_RegWrite)
{
case REGWRITE_VALE:
{
ID_EX.VRs1 = EX_MEM.ALU_out;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = EX_MEM.ALU_out\n");
#endif
}
break;
case REGWRITE_VALM:
{
StageMode[STAGE_EX] = MODE_BUBBLE;
LoadUseHazardCount++;
}
break;
case REGWRITE_VALP:
{
ID_EX.VRs1 = ID_EX_old.NextPC;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = ID_EX_old.NextPC\n");
#endif
}
break;
default:
ERROR(__LINE__);
}
}
else if (StageModeOld[STAGE_MEM] == MODE_LOAD &&
IF_ID_old.RegRs1 == EX_MEM_old.RegDst)
{
switch (EX_MEM_old.Ctrl_WB_RegWrite)
{
case REGWRITE_VALE:
{
ID_EX.VRs1 = EX_MEM_old.ALU_out;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = EX_MEM_old.ALU_out\n");
#endif
}
break;
case REGWRITE_VALM:
{
ID_EX.VRs1 = MEM_WB.Mem_read;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = MEM_WB.Mem_read\n");
#endif
}
break;
case REGWRITE_VALP:
{
ID_EX.VRs1 = EX_MEM_old.NextPC;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = EX_MEM_old.NextPC\n");
#endif
}
break;
default:
ERROR(__LINE__);
}
}
else if (StageModeOld[STAGE_WB] == MODE_LOAD &&
IF_ID_old.RegRs1 == MEM_WB_old.RegDst)
{
switch (MEM_WB_old.Ctrl_WB_RegWrite)
{
case REGWRITE_VALE:
{
ID_EX.VRs1 = MEM_WB_old.ALU_out;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = MEM_WB_old.ALU_out\n");
#endif
}
break;
case REGWRITE_VALM:
{
ID_EX.VRs1 = MEM_WB_old.Mem_read;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = MEM_WB_old.Mem_read\n");
#endif
}
break;
case REGWRITE_VALP:
{
ID_EX.VRs1 = MEM_WB_old.NextPC;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs1 = MEM_WB_old.NextPC\n");
#endif
}
break;
default:
ERROR(__LINE__);
}
}
}
if (IF_ID_old.RegRs2 != R_zero)
{
if ((StageModeOld[STAGE_EX] == MODE_LOAD || wait_finish_flag) &&
IF_ID_old.RegRs2 == ID_EX_old.RegDst)
{
switch (ID_EX_old.Ctrl_WB_RegWrite)
{
case REGWRITE_VALE:
{
ID_EX.VRs2 = EX_MEM.ALU_out;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = EX_MEM.ALU_out\n");
#endif
}
break;
case REGWRITE_VALM:
{
StageMode[STAGE_EX] = MODE_BUBBLE;
LoadUseHazardCount++;
}
break;
case REGWRITE_VALP:
{
ID_EX.VRs2 = ID_EX_old.NextPC;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = ID_EX_old.NextPC\n");
#endif
}
break;
default:
ERROR(__LINE__);
}
}
else if (StageModeOld[STAGE_MEM] == MODE_LOAD &&
IF_ID_old.RegRs2 == EX_MEM_old.RegDst)
{
switch (EX_MEM_old.Ctrl_WB_RegWrite)
{
case REGWRITE_VALE:
{
ID_EX.VRs2 = EX_MEM_old.ALU_out;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = EX_MEM_old.ALU_out\n");
#endif
}
break;
case REGWRITE_VALM:
{
ID_EX.VRs2 = MEM_WB.Mem_read;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = MEM_WB.Mem_read\n");
#endif
}
break;
case REGWRITE_VALP:
{
ID_EX.VRs2 = EX_MEM_old.NextPC;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = EX_MEM_old.NextPC\n");
#endif
}
break;
default:
ERROR(__LINE__);
}
}
else if (StageModeOld[STAGE_WB] == MODE_LOAD &&
IF_ID_old.RegRs2 == MEM_WB_old.RegDst)
{
switch (MEM_WB_old.Ctrl_WB_RegWrite)
{
case REGWRITE_VALE:
{
ID_EX.VRs2 = MEM_WB_old.ALU_out;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = MEM_WB_old.ALU_out\n");
#endif
}
break;
case REGWRITE_VALM:
{
ID_EX.VRs2 = MEM_WB_old.Mem_read;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = MEM_WB_old.Mem_read\n");
#endif
}
break;
case REGWRITE_VALP:
{
ID_EX.VRs2 = MEM_WB_old.NextPC;
BypassCount++;
#ifdef PRINT_BYPASS
printf("Bypass: ID_EX.VRs2 = MEM_WB_old.NextPC\n");
#endif
}
break;
default:
ERROR(__LINE__);
}
}
}
}
#else
if (StageModeOld[STAGE_ID] != MODE_BUBBLE &&
((IF_ID_old.RegRs1 != R_zero &&
(((StageModeOld[STAGE_EX] == MODE_LOAD || wait_finish_flag) &&
IF_ID_old.RegRs1 == ID_EX_old.RegDst) ||
(StageModeOld[STAGE_MEM] == MODE_LOAD && IF_ID_old.RegRs1 == EX_MEM_old.RegDst) ||
(StageModeOld[STAGE_WB] == MODE_LOAD && IF_ID_old.RegRs1 == MEM_WB_old.RegDst))) ||
(IF_ID_old.RegRs2 != R_zero &&
(((StageModeOld[STAGE_EX] == MODE_LOAD || wait_finish_flag) &&
IF_ID_old.RegRs2 == ID_EX_old.RegDst) ||
(StageModeOld[STAGE_MEM] == MODE_LOAD && IF_ID_old.RegRs2 == EX_MEM_old.RegDst) ||
(StageModeOld[STAGE_WB] == MODE_LOAD &&
IF_ID_old.RegRs2 == MEM_WB_old.RegDst))))) // data hazard
{
StageMode[STAGE_EX] = MODE_BUBBLE;
}
#endif
if (Mispredicted) // mispredicted PC
{
StageMode[STAGE_ID] = MODE_BUBBLE;
StageMode[STAGE_EX] = MODE_BUBBLE;
MispredictedCount++;
}
if (ALUWait > 0) // wait for division
{
StageMode[STAGE_MEM] = MODE_BUBBLE;
}
// update intermediate registers
if (StageModeOld[STAGE_IF] != MODE_STALL)
IF_ID_old = IF_ID;
if (StageModeOld[STAGE_ID] != MODE_STALL)
ID_EX_old = ID_EX;
if (StageModeOld[STAGE_EX] != MODE_STALL)
EX_MEM_old = EX_MEM;
if (StageModeOld[STAGE_MEM] != MODE_STALL)
MEM_WB_old = MEM_WB;
// update cycle conunt
CycleCount += 1;
// calculate CPI
CPI = (float)CycleCount / (float)InstCount;
#ifdef PREDICT
// calculate predictive accuracy
PredictiveAccuracy = (float)PredictCorrectCount / (float)PredictableCount;
#endif
if (exit_flag != 0)
return false;
return true;
}
void ERROR(int line)
{
printf("ERROR!: %d\n", line);
}
void IF()
{
switch (StageMode[STAGE_IF])
{
case MODE_STALL:
{
#ifdef PRINT_MODE
printf("STALL IF\n");
#endif
return;
}
break;
case MODE_BUBBLE:
{
#ifdef PRINT_MODE
printf("BUBBLE IF\n");
#endif
IF_ID.RegDst = R_zero;
IF_ID.RegRs1 = R_zero;
IF_ID.RegRs2 = R_zero;
IF_ID.InstPC = 0;
IF_ID.NextPC = 0;
IF_ID.EXTBit = 0;
IF_ID.EXTSrc = 0;
IF_ID.Ctrl_ID_EXTOp = EXTOP_SIGNED;
IF_ID.Ctrl_EX_BranchCmp = BRANCHCMP_NOP;
IF_ID.Ctrl_EX_ALUSrc = ALUSRC_NONE;
IF_ID.Ctrl_EX_ALUOp = ALUOP_NOP;
IF_ID.Ctrl_EX_Branch = BRANCH_NO;
IF_ID.Ctrl_EX_PredictedBranch = BRANCH_NO;
IF_ID.Ctrl_MEM_MemWrite = MEMWRITE_NO;
IF_ID.Ctrl_MEM_MemRead = MEMREAD_NO;
IF_ID.Ctrl_WB_RegWrite = REGWRITE_NO;
return;
}
break;
default:
break;
}
ULL InstPC = PC;
REG NextPC = 0;
unsigned int Inst = 0;
unsigned char InstSize = INSTSIZE_32;
unsigned char EXTOp = EXTOP_SIGNED;
unsigned int EXTBit = 0;
unsigned int EXTSrc = 0;
unsigned char ALUOp = ALUOP_NOP, ALUSrc = ALUSRC_NONE, BranchCmp = BRANCHCMP_NOP;
unsigned char MemRead = MEMREAD_NO, MemWrite = MEMWRITE_NO;
unsigned char RegWrite = REGWRITE_NO;
unsigned char Branch = BRANCH_NO, PredictedBranch = BRANCH_NO;
// instruction sections
unsigned int rs1 = R_zero, rs2 = R_zero, rd = R_zero;
unsigned int opcode = 0;
unsigned int funct3 = 0, funct7 = 0;
unsigned int imm0_11 = 0;
unsigned int imm12_31 = 0;
unsigned int imm6_11 = 0;
unsigned int imm5_11 = 0;
unsigned int imm0_5 = 0;
unsigned int imm0_4 = 0;
// fetch instructor
Inst = READ_WORD(InstPC);
if ((Inst & 0x3) != 0x3)
{
InstSize = INSTSIZE_16;
NextPC = InstPC + 2;
}
else
{
InstSize = INSTSIZE_32;
NextPC = InstPC + 4;
}
// indentify instructor
if (InstSize == INSTSIZE_16)
{
opcode = GET_BITS(Inst, 0, 1);
funct3 = GET_BITS(Inst, 13, 15);
switch (opcode)
{
case OPC_00:
{
rs1 = RVC_TO_R(GET_BITS(Inst, 7, 9));
switch (funct3)
{
case F3C_ADDI4SPN:
{
rd = RVC_TO_R(GET_BITS(Inst, 2, 4));
rs1 = R_sp;
EXTSrc = (GET_BITS(Inst, 7, 10) << 6) |
(GET_BITS(Inst, 11, 12) << 4) |
(GET_BIT(Inst, 5) << 3) |
(GET_BIT(Inst, 6) << 2);
EXTBit = 10;
EXTOp = EXTOP_UNSIGED;
ALUOp = ALUOP_ADD;
ALUSrc = ALUSRC_RS1_IMM;
RegWrite = REGWRITE_VALE;
sprintf(InstBuf, "addi %s, %s, %lld", R_NAME[rd],
R_NAME[rs1],
EXT_UNSIGNED_DWORD(EXTSrc, EXTBit));
}
break;
case F3C_LW:
{
rd = RVC_TO_R(GET_BITS(Inst, 2, 4));
EXTSrc = (GET_BIT(Inst, 5) << 6) |
(GET_BITS(Inst, 10, 12) << 3) |
(GET_BIT(Inst, 6) << 2);
EXTBit = 7;
EXTOp = EXTOP_UNSIGED;
ALUOp = ALUOP_ADD;
ALUSrc = ALUSRC_RS1_IMM;
MemRead = MEMREAD_WORD;
RegWrite = REGWRITE_VALM;
sprintf(InstBuf, "lw %s, %lld(%s)", R_NAME[rd],
EXT_UNSIGNED_DWORD(EXTSrc, EXTBit),
R_NAME[rs1]);
}
break;
case F3C_LD:
{
rd = RVC_TO_R(GET_BITS(Inst, 2, 4));
EXTSrc = (GET_BITS(Inst, 5, 6) << 6) |
(GET_BITS(Inst, 10, 12) << 3);
EXTBit = 8;
EXTOp = EXTOP_UNSIGED;
ALUSrc = ALUSRC_RS1_IMM;
MemRead = MEMREAD_DWORD;
RegWrite = REGWRITE_VALM;
sprintf(InstBuf, "ld %s, %lld(%s)", R_NAME[rd],
EXT_UNSIGNED_DWORD(EXTSrc, EXTBit),
R_NAME[rs1]);
}
break;
case F3C_SW:
{
rs2 = RVC_TO_R(GET_BITS(Inst, 2, 4));
EXTSrc = (GET_BIT(Inst, 5) << 6) |
(GET_BITS(Inst, 10, 12) << 3) |
(GET_BIT(Inst, 6) << 2);
EXTBit = 7;
EXTOp = EXTOP_UNSIGED;
ALUOp = ALUOP_ADD;
ALUSrc = ALUSRC_RS1_IMM;
MemWrite = MEMWRITE_WORD;
sprintf(InstBuf, "sw %s, %lld(%s)", R_NAME[rs2],
EXT_UNSIGNED_DWORD(EXTSrc, EXTBit),
R_NAME[rs1]);
}
break;
case F3C_SD:
{
rs2 = RVC_TO_R(GET_BITS(Inst, 2, 4));
EXTSrc = (GET_BITS(Inst, 5, 6) << 6) |
(GET_BITS(Inst, 10, 12) << 3);
EXTBit = 8;
EXTOp = EXTOP_UNSIGED;
ALUOp = ALUOP_ADD;
ALUSrc = ALUSRC_RS1_IMM;
MemWrite = MEMWRITE_WORD;
sprintf(InstBuf, "sd %s, %lld(%s)", R_NAME[rs2],
EXT_UNSIGNED_DWORD(EXTSrc, EXTBit),
R_NAME[rs1]);
}
break;
default:
ERROR(__LINE__);
}
}
break;
case OPC_01:
{
switch (funct3)
{
case F3C_ADDI:
{
rd = GET_BITS(Inst, 7, 11);
rs1 = rd;
EXTSrc =
(GET_BIT(Inst, 12) << 5) | (GET_BITS(Inst, 2, 6));
EXTBit = 6;
ALUOp = ALUOP_ADD;
ALUSrc = ALUSRC_RS1_IMM;
RegWrite = REGWRITE_VALE;
sprintf(InstBuf, "addi %s, %s, %lld", R_NAME[rd],
R_NAME[rd], EXT_SIGNED_DWORD(EXTSrc, EXTBit));
}
break;
case F3C_ADDIW:
{
rd = GET_BITS(Inst, 7, 11);
rs1 = rd;
EXTSrc =
(GET_BIT(Inst, 12) << 5) | (GET_BITS(Inst, 2, 6));
EXTBit = 6;
ALUOp = ALUOP_ADDW;
ALUSrc = ALUSRC_RS1_IMM;
RegWrite = REGWRITE_VALE;
sprintf(InstBuf, "addiw %s, %s, %lld", R_NAME[rd],
R_NAME[rd], EXT_SIGNED_DWORD(EXTSrc, EXTBit));
}
case F3C_LI:
{
rd = GET_BITS(Inst, 7, 11);
HINT(rd == 0);
rs1 = R_zero;
EXTSrc =
(GET_BIT(Inst, 12) << 5) | (GET_BITS(Inst, 2, 6));
EXTBit = 6;
ALUSrc = ALUSRC_RS1_IMM;
ALUOp = ALUOP_ADD;
RegWrite = REGWRITE_VALE;
sprintf(InstBuf, "li %s, %lld", R_NAME[rd],
EXT_SIGNED_DWORD(EXTSrc, EXTBit));
}
break;
case F3C_LUI:
{
rd = GET_BITS(Inst, 7, 11);
HINT(rd == 0);
if (rd != R_sp) // C.LUI
{
rs1 = R_zero;
EXTSrc = (GET_BIT(Inst, 12) << 17) |
(GET_BITS(Inst, 2, 6) << 12);
EXTBit = 18;
ALUSrc = ALUSRC_RS1_IMM;
ALUOp = ALUOP_ADD;
RegWrite = REGWRITE_VALE;
sprintf(InstBuf, "lui %s, %lld", R_NAME[rd],
(EXT_SIGNED_DWORD(EXTSrc, EXTBit)));
}
else // C.ADDI16SPN
{
rs1 = rd;
EXTSrc = (GET_BIT(Inst, 12) << 9) |
(GET_BITS(Inst, 3, 4) << 7) |
(GET_BIT(Inst, 5) << 6) |
(GET_BIT(Inst, 2) << 5) |
(GET_BIT(Inst, 6) << 4);
EXTBit = 10;
ALUOp = ALUOP_ADD;
ALUSrc = ALUSRC_RS1_IMM;
RegWrite = REGWRITE_VALE;
sprintf(InstBuf, "addi %s, %s, %lld",
R_NAME[rd], R_NAME[rd],
EXT_SIGNED_DWORD(EXTSrc, EXTBit));
}
}
break;
case F3C_ARIT:
{
unsigned int funct2_1 = GET_BITS(Inst, 10, 11);
switch (funct2_1)
{
case F2C_1_SRLI:
{
rd = RVC_TO_R(GET_BITS(Inst, 7, 9));
rs1 = rd;
EXTSrc = (GET_BIT(Inst, 12) << 5) |
(GET_BITS(Inst, 2, 6));
EXTBit = 6;
ALUOp = ALUOP_SRL;
ALUSrc = ALUSRC_RS1_IMM;
RegWrite = REGWRITE_VALE;
sprintf(
InstBuf, "srli %s, %s, %lld",
R_NAME[rd], R_NAME[rd],
EXT_SIGNED_DWORD(EXTSrc, EXTBit));
}
break;
case F2C_1_SRAI:
{
rd = RVC_TO_R(GET_BITS(Inst, 7, 9));
rs1 = rd;
EXTSrc = (GET_BIT(Inst, 12) << 5) |
(GET_BITS(Inst, 2, 6));
EXTBit = 6;
ALUOp = ALUOP_SRA;
ALUSrc = ALUSRC_RS1_IMM;
RegWrite = REGWRITE_VALE;
sprintf(
InstBuf, "srai %s, %s, %lld",
R_NAME[rd], R_NAME[rd],
EXT_SIGNED_DWORD(EXTSrc, EXTBit));
}
break;
case F2C_1_ANDI:
{
rd = RVC_TO_R(GET_BITS(Inst, 7, 9));
rs1 = rd;
EXTSrc = (GET_BIT(Inst, 12) << 5) |
(GET_BITS(Inst, 2, 6));
EXTBit = 6;
ALUOp = ALUOP_AND;
ALUSrc = ALUSRC_RS1_IMM;
RegWrite = REGWRITE_VALE;
sprintf(
InstBuf, "andi %s, %s, %lld",
R_NAME[rd], R_NAME[rd],
EXT_SIGNED_DWORD(EXTSrc, EXTBit));
}
break;
case F2C_1_REG:
{
unsigned int funct1 = GET_BIT(Inst, 12);
unsigned int funct2_2 =
GET_BITS(Inst, 5, 6);
rd = RVC_TO_R(GET_BITS(Inst, 7, 9));
rs1 = rd;
rs2 = RVC_TO_R(GET_BITS(Inst, 2, 4));
ALUSrc = ALUSRC_RS1_RS2;
RegWrite = REGWRITE_VALE;
switch (funct1)
{
case F1C_D:
{
switch (funct2_2)
{
case F2C_2_SUB:
{
ALUOp =
ALUOP_SUB;
sprintf(
InstBuf,
"su"
"b"
" "
"%s"
", "
"%s"
", "
"%"
"s",
R_NAME
[rd],
R_NAME
[rd],
R_NAME
[rs2]);
}
break;
case F2C_2_XOR:
{
ALUOp =
ALUOP_XOR;
sprintf(
InstBuf,
"xo"
"r "
" %"
"s,"
" %"
"s,"
" %"
"s",
R_NAME
[rd],
R_NAME
[rd],
R_NAME
[rs2]);
}
break;
case F2C_2_OR:
{
ALUOp =
ALUOP_OR;
sprintf(
InstBuf,
"or"
" "
"%s"
", "
"%s"
", "
"%"
"s",
R_NAME
[rd],
R_NAME
[rd],
R_NAME
[rs2]);
}
break;
case F2C_2_AND:
{
ALUOp =
ALUOP_AND;
sprintf(
InstBuf,
"an"
"d "
" %"
"s,"
" %"
"s,"
" %"
"s",
R_NAME
[rd],
R_NAME
[rd],
R_NAME
[rs2]);
}
break;
default:
ERROR(
__LINE__);
}
}
break;
case F1C_W:
{
switch (funct2_2)
{
case F2C_2_SUBW:
{
ALUOp =
ALUOP_SUBW;
sprintf(
InstBuf,
"su"
"bw"
" "
"%s"
", "
"%s"
", "
"%"
"s",
R_NAME
[rd],
R_NAME
[rd],
R_NAME
[rs2]);
}
break;
case F2C_2_ADDW:
{
ALUOp =
ALUOP_ADDW;
sprintf(
InstBuf,
"ad"
"dw"
" "
"%s"
", "
"%s"
", "
"%"
"s",
R_NAME
[rd],
R_NAME
[rd],
R_NAME
[rs2]);
}
break;
default:
ERROR(
__LINE__);
}
}
break;
default:
ERROR(__LINE__);
}
}
break;
default:
ERROR(__LINE__);
}
}
break;
case F3C_J:
{
EXTSrc =
(GET_BIT(Inst, 12) << 11) |
(GET_BIT(Inst, 8) << 10) |
(GET_BITS(Inst, 9, 10) << 8) |
(GET_BIT(Inst, 6) << 7) | (GET_BIT(Inst, 7) << 6) |
(GET_BIT(Inst, 2) << 5) | (GET_BIT(Inst, 11) << 4) |
(GET_BITS(Inst, 3, 5) << 1);
EXTBit = 12;
ALUSrc = ALUSRC_PC_IMM;
ALUOp = ALUOP_ADD;
Branch = BRANCH_YES;
sprintf(InstBuf, "jal %s, 0x%llx", R_NAME[R_zero],
EXT_SIGNED_DWORD(EXTSrc, EXTBit) + PC);
}
break;
case F3C_BEQZ:
{
rs1 = RVC_TO_R(GET_BITS(Inst, 7, 9));
rs2 = R_zero;
EXTSrc = (GET_BIT(Inst, 12) << 8) |
(GET_BITS(Inst, 5, 6) << 6) |
(GET_BIT(Inst, 2) << 5) |
(GET_BITS(Inst, 10, 11) << 3) |
(GET_BITS(Inst, 3, 4) << 1);
EXTBit = 9;
BranchCmp = BRANCHCMP_EQ;
ALUSrc = ALUSRC_PC_IMM;
ALUOp = ALUOP_ADD;
sprintf(InstBuf, "beqz %s, %s, 0x%llx", R_NAME[rs1],
R_NAME[rs2],