Skip to content
View FedeCappe95's full-sized avatar
2 followers · 2 following
  • Pisa, Italy

Achievements

Achievement: Arctic Code Vault Contributor

Achievements

Achievement: Arctic Code Vault Contributor

Block or report FedeCappe95

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
FedeCappe95/README.md

Hi there, I'm Cappe 👋


Something about me

  • 🎓 Student in Computer Engineering - Cybersecuruty at University of Pisa
  • 🏐 Volleyball player
  • 🌱 I like GUIs, web technologies, front-end things, etc, but
  • 👯 I really like those ingenious middleware technologies and
  • 🥅 I love low-level stuff!
  • ⚡ Add the passion for electronics...
  • 🤯 Yep, I'm also that kind of guy who plays with an Arduino!

Beyond my repositories

Bachelor's Degree: Ingegneria Informatica

University of Pisa. Final mark: 110/110.
• Thesis: "Implementazione su piattaforma NetLogo dell'algoritmo Particle Swarm Optimization for Robot Recruitment (PSO-RR)"

Master Degree: Computer Engineering, Cybersecurity

Univeristy of Pisa. Final mark: 110/110 L
• Thesis: "Distributed intrusion detection in cloud data centers"

Other stuff

  • Web developer
  • Projects in large-scale databases and cloud computing technologies
  • CappeKernel (my own kernel for AMD64 computers for educational purposes)
  • Game modder (Minecraft, Skyrim and Dragonball Z Budokai Tenkaichi 3 on PlayStation 2)

Languages and Tools:

C C++ Java JavaScript Python Node.js Erlang HTML5 CSS3 MySQL MongoDB Neo4J RabbitMQ Kali Terminal



Top Langs


Repos Badge Commits Badge

Popular repositories Loading

  1. CIC-filter-VHDL CIC-filter-VHDL Public

    Progetto universitario. Realizzazione in VHDL, test e sintesi con Xilinx Vivado per FPGA di un CIC filter.

    VHDL 1

  2. GapWatcherProto2 GapWatcherProto2 Public

    Java

  3. Task3 Task3 Public

    Inspired by the fight against the Covid-19 pandemic, the aim of the project is to track the movement of a large number of people and calculate a risk index for each of them based on their movements…

    Java

  4. OpportunisticCellularNetworkSimulator OpportunisticCellularNetworkSimulator Public

    A simulator of an opportunistic scheduling algorithm in a simplified 4G cell, using the Omnet++ framework

    C++

  5. FedeCappe95 FedeCappe95 Public

  6. qemu qemu Public

    Forked from vmaffione/qemu

    qemu fork adding netmap passthrough networking, e1000 paravirtualized adapter, and VMPI support

    C