Implementation of a MIPS Deluxe design processor using FPGA.
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The objective of this project was to put into practice the knowledge acquired during the "Computer Architecture" course regarding the internal design of processors, components, and how they interact with assembly code.
For a comprehensive analysis of the project, it is proposed to review the academic report, which contains all the theoretical concepts, design decisions and use of the project.
This project was developed using Xilinx Vivado Tool and the Nexys 4 DDR FPGA. To send the binary file to the FPGA, the software Realterm was used.
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Clone the repository using the command
git clone git@github.com:Fran-cio/mipsDesign.git --recursive. This command not only clones the repository with the MIPS sources but also initializes the submodules used within the project.Submodules:
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Create a new project in Vivado.
WARNING: Do not add the sources yet!
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Once the project is created, proceed to add the folder with the sources, as well as the simulation files if desired.
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Add the constraints (located in the folder
FPGA-MIPS/Mips.srcs/constrs_1) and the .xci file corresponding to the IP of the clock tree (located in the folderFPGA-MIPS/Mips.srcs/ip/clk_wiz_0/clk_wiz_0.xci). -
Run "generate bitstream" in Vivado.
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Connect the board.
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Click on "AutoConnect".
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Click on "Program device". Once programmed, you should see a red light on the board.
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At this point, we have the MIPS synthesis loaded on the board, so we proceed to download RealTerm. This app will allow us to send data via serial to the board.
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In the "port" tab, set the baud rate to 9600 and choose the corresponding port.
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OPTIONAL: In the "send" tab, you can send a "P" to see if it returns 0 and thus check that the serial connection has been established correctly.
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Now we need to generate the binary. To do this, go to
FPGA-MIPS/python_src. There you will find a .asm file called src_code.asm. Place the desired assembly code there. In the same folder, you will also find test files with their respective analyses. -
In this step, we generate the binary. Run
python3 -W ignore assembler.py. This will generate a .hex file named output_code.hex.DISCLAIMER: You may need to install some Python modules if you don't have them. Follow the terminal logs in such case.
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Now we proceed to load the binary. In the "send" tab of RealTerm, send a letter 'B'.
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Now copy and paste the binary, or import it into the corresponding section in RealTerm.
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When the binary is successfully loaded, you should see a green light on the board.
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Now you can follow the commands and state machine presented in the report to perform the desired execution. For example, you could send a 'G' to run the entire program. In that case, you would see a blue light when the execution finishes.
DISCLAIMER: LED colors may vary depending on the board used or if constraints are modified.
There are three additional requirements related to the interaction between the processor and the user. For this purpose, the Super Unit of Operation and Debug (SUOD) was designed. It serves as a large state machine that generates actions based on user input.
The SUOD (System User Operation Device) is a unit that provides a main menu type interface for project execution. It has a set of commands received via UART (Universal Asynchronous Receiver-Transmitter) and performs a set of actions.
Commands:
| Command | Description |
|---|---|
| "G" | Run mode, executes the loaded program. |
| "B" | Enters "BootLoader" mode to receive binary until a halt instruction is received. |
| "S" | Advances one clock cycle. |
| "P" | Returns the value of the Program Counter (PC). |
| "C" | Resets the program. |
| "T" | Increments the register pointer. |
| "R" | Returns the value of the pointed register space. |
| "E" | Decrements the register pointer. |
| "," | Increments the memory pointer. |
| "M" | Returns the value of the pointed memory space. |
| "N" | Decrements the memory pointer. |
| "F" | Clears the loaded program. |
| Category | Instruction | Type | Example | Comment |
|---|---|---|---|---|
| Arithmetic | ADDU | R | addu $s1,$s2,$s3 | Unsigned addition between registers |
| SUBU | R | sub $s1,$s2,$s3 | Unsigned subtraction between registers | |
| ADDI | I | addi $s1,$s2,20 | Immediate addition | |
| Information Transfer | LB | I | lb $s1,20($s2) | Load Byte |
| LH | I | lh $s1,20($s2) | Load Half | |
| LW | I | lw $s1,20($s2) | Load Word | |
| LWU | I | lwu $s1,20($s2) | Load Word Unsigned | |
| LBU | I | lbu $s1,20($s2) | Load Byte Unsigned | |
| LHU | I | lhu $s1,20($s2) | Load Half Unsigned | |
| SB | I | sb $s1,20($s2) | Store Byte | |
| SH | I | sh $s1,20($s2) | Store Half | |
| SW | I | sw $s1,20($s2) | Store Word | |
| LUI | I | lui $s1,20 | Load Upper Immediate | |
| Logic | SLL | R | sll $s1,$s2,10 | Shift Left Logical |
| SRL | R | srl $s1,$s2,10 | Shift Right Logical | |
| SRA | R | sra $s1,$s2,10 | Shift Right Arithmetic | |
| SLLV | R | sllv $s1,$s2,10 | Shift Left Logical Immediate | |
| SRLV | R | srlv $s1,$s2,10 | Shift Right Logical Immediate | |
| SRAV | R | srav $s1,$s2,10 | Shift Right Arithmetic Immediate | |
| AND | R | and $s1,$s2,$s3 | AND operation | |
| OR | R | or $s1,$s2,$s3 | OR operation | |
| XOR | R | xor $s1,$s2,$s3 | XOR operation | |
| NOR | R | nor $s1,$s2,$s3 | NOR operation | |
| SLT | R | slt $s1,$s2,$s3 | Set Less Than | |
| ANDI | I | andi $s1,$s2,20 | Immediate AND operation | |
| ORI | I | ori $s1,$s2,20 | Immediate OR operation | |
| XORI | I | xori $s1,$s2,20 | Immediate XOR operation | |
| SLTI | I | slti $s1,$s2,20 | Set Less Than Immediate | |
| Conditional Jump | BEQ | I | beq $s1,$s2,25 | Branch if Equal |
| BNE | I | bne $s1,$s2,25 | Branch if Not Equal | |
| Unconditional Jump | JR | I | jr $ra | Jump to Register Address |
| JALR | I | jalr $s1,s10 | Jump to Register Address and Link | |
| J | J | j 2500 | Jump to Immediate Address | |
| JAL | J | jal 2500 | Jump to Immediate Address and Link | |
| HALT | H | halt | Halt Instruction |
Contributions are what make the open source community such an amazing place to learn, inspire, and create. Any contributions you make are greatly appreciated.
If you have a suggestion that would make this better, please fork the repo and create a pull request. You can also simply open an issue with the tag "enhancement". Don't forget to give the project a star! Thanks again!
- Fork the Project
- Create your Feature Branch (
git checkout -b feature/AmazingFeature) - Commit your Changes (
git commit -m 'Add some AmazingFeature') - Push to the Branch (
git push origin feature/AmazingFeature) - Open a Pull Request
Distributed under the Beerware License🍻. See LICENSE.txt for more information.
Francisco Ciordia Cantarella - francisco.ciordia.cantarella@gmail.com
Project Link: https://github.com/Fran-Cio/mipsDesign
Patterson, David A., and John L. Hennessy. Computer Organization and Design MIPS Edition: The Hardware/Software Interface. Edited by David A. Patterson and John L. Hennessy, Elsevier Science, 2014. Accessed 27 January 2023.