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  (text "DRAM addressing in brief: RAS, dram_addr_sel and CAS are generated in memory management sheet.\n- DRAM is organized as a square matrix, so its 64k addressing space is splitted in 8 address bits\n  used both for row and column address. 2^8 * 2^8 = 64k.\n- RAS is used to sample RA (RAM Address) as row address.\n- CAS is used to sample RA as column address.\n- CAS is a delayed dram_addr_sel pulse, which is a delayed RAS pulse. This way, through J2/J3 multiplexers,\n  row and column address can be fed into RA and correctly sampled.\n- CAS and dram_addr_sel are idle when refresh is done (RAS only refresh mode)."
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  (text "- generated parity is fed into Din of a separate DRAM memory IC.\n- stored parity parity_q (Dout) is fed into generator/validator\n  only during memory reads.\n- while validating, parity_d = parity error. Its value is registered\n  in xxx latch and makes a LED turn on (and probably send an IRQ to Z80?)"
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  (text "Enabled only during\nDRAM reads" (at 180.34 114.3 0)
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    (uuid 0a829e92-ebb6-48d7-b938-aa537581eb38)
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    (uuid 0ceb7d24-c4c1-4218-a99e-9152a6ba0d77)
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