Verilog-HDL

This repository contains a few codes of Verilog HDL that gives you a fair knowledge about this language

Name		Name	Last commit message	Last commit date
Latest commit History 44 Commits
2 to 4 Decoder.v		2 to 4 Decoder.v
4 to 2 Priority Encoder.v		4 to 2 Priority Encoder.v
4-bit FA in 4:1 MUX.v		4-bit FA in 4:1 MUX.v
512-Bit Adder.v		512-Bit Adder.v
74LS138.v		74LS138.v
BCD 100 Adder.v		BCD 100 Adder.v
Basic_gates.v		Basic_gates.v
Bit reversal using "for" loop.v		Bit reversal using "for" loop.v
Dual Port RAM		Dual Port RAM
Hack_ALU.v		Hack_ALU.v
IC74LS147N.v		IC74LS147N.v
LICENSE		LICENSE
Minimum of 4 numbers(1).v		Minimum of 4 numbers(1).v
Minimum of 4 numbers(2).v		Minimum of 4 numbers(2).v
Multiplier 4x4.v		Multiplier 4x4.v
N-bit full adder using "generate-loop" statement.v		N-bit full adder using "generate-loop" statement.v
Parity.v		Parity.v
README.md		README.md
Single Port RAM		Single Port RAM
popcount.v		popcount.v

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