add force_greedy_sample #704
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Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com> Signed-off-by: Chendi Xue <chendi.xue@intel.com>
…roject#630) ``` VLLM_TP_SPLIT_SIZE_BY_SEQ=2 VLLM_TP_SPLIT_SIZE_BY_BATCH=2 ``` Signed-off-by: Kunshang Ji <kunshang.ji@intel.com> Signed-off-by: Chendi Xue <chendi.xue@intel.com> Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
https://jira.habana-labs.com/browse/SW-212933 ``` VLLM_PIPELINED_PA=true \ VLLM_SOFTMAX_CONST_NORM=true ``` Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Enable splitting qkv and gate_up into separate columnparallellinear layers, instead of overwriting qkvparallellinear and mergedcolumnparallellinear layers. --------- Signed-off-by: Chendi Xue <chendi.xue@intel.com> Co-authored-by: Kunshang Ji <kunshang.ji@intel.com> Co-authored-by: Chendi Xue <chendi.xue@intel.com> Co-authored-by: Barak Goldberg <bgoldberg@habana.ai> Co-authored-by: Nir David <ndavid@habana.ai>
Signed-off-by: Kunshang <kunshangli@habana.ai>
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madamczykhabana,
michalkuligowski and
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xuechendi
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