Quartus project references files that don't exist

[d3x0r]

https://github.com/HerrNamenlos123/JTAG_Interface/blob/master/FPGA/projects/example_simple/MKRVIDOR4000.qsf#L100-L103

set_global_assignment -name VERILOG_FILE jtag_interface8.v
set_global_assignment -name VERILOG_FILE jtag_interface4.v
set_global_assignment -name VERILOG_FILE jtag_interface2.v
set_global_assignment -name VERILOG_FILE jtag_interface16.v

those should be 7,3,?,15 and add 31 instead?

[HerrNamenlos123]

I am not exactly sure what the issue is. .qsf is an auto-generated file from Quartus if I am not mistaken, right?
These lines definitely haven't been written by me. Unfortunately I don't have Quartus installed right now to check anything.
So if there is an issue, could you please elaborate more about what exactly the problem is?

[d3x0r]

Well... those files show up in the files list... This is after adding the other files and my own counter back in... and reverting so the even numbered interfaces show...

This is just a new thing to me, so I'm not entirely sure what the flow of things are. In the MyDesign file there are symbols for interface3, 7,15 etc... not sure how they are there, unless maybe the file name maybe didn't use to match? I had to add mine as a counter.v file and compile before it showed as a symbol I could use in the MyDesign.bdf editor...
Since they show up in the files list - you can't edit them ... you get

So, to me, it looks like there would have to be errors... but somehow the design actually knows the other interfaces anyway.

I understand that's not a file that you edit and that it's managed by Quartus... it still points to files that don't exist.