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This is the 2nd version of HICANN neuromorphic hardware and the successor of spikey. The neurons are implementations of conductance based AdEX or LIF type based on their physical equations with adjustable analog settings (AdEx). The system does not provide either short time or spike timing dependent plasticity rules because of hardware issues. The synaptic weights can be adjusted by 4-bit integers.
The system is either arranged as a single chip holding 8 HICANNs with 512 neurons each or on wafer basis extending the amount of HICANNs to 48 with again 512 neurons each. The large system consists of 20 wafer holding 384 chips. So in total the entire system on wafer basis has around 4 million neurons with 1 billion synapses. The time constants in the system are 10^4 times smaller than in biology. The analog parameters of the neurons are calibrated once to limit neuron to neuron variability. However this process takes time and therefore only 6 chips of one wafer are calibrated (19.4.2017). Loading analog parameters on the chip, such as configuring the membrane resting potential, together with calibration parameters takes time. Thus, one should avoid to change these parameters during any simulation in order prevent loss of speedup. Important is to consider that loading new analog parameters is responsible for trial to trial variability: < 5% trial to trial variance for potentials and < 20% for time parameters. However, loaded analog parameters decay.
One membrane potential as well as all spike times can be read out after an experiment has finished. Thus, to implement a weight update rule, one is constrained to use only spike timings and carry out the weight update offline with hardware simulation in a loop. In the the current HW status (19.4.2017) 4 neurons are usually combined together to form a more stable unit.
This is the newest technology currently used in Heidelberg and it implements a digital learning system (DLS). It is the third generation of the chips in Heidelberg and manufactured with 65nm technology in contrast to the previous 180nm HICANN systems. Currently (20.04.2017), it is at an early development stage with four prototype boards at the laboratory in Heidelberg, but more board are planned. The planned release date of this platform is expected in 2019. The prototype chip comprises 32 neurons which are of current based AdEx type. Each neuron has included a spike counter. Synapses are arranged in an array of 32x32 on chip where each synapse can assume a weight of 6 bit resolution. Each synapse also features correlation sensors that relate pre- and postsynaptic spikes for both causal and acausal dependence.
Plasticity: The system adds plasticity functionality by its digital learning system. It consists of an on chip microcontroller with access to the weights in the synapse array, correlation sensors, spike counter, a vector processor and 16k RAM. The on chip microcontroller can be programmed to update all synapse weights according to any programmable update rule. Available information to this update rule are the values of the correlation sensors, the spike counter values as well as the current weights. Any implementation of an update rule needs to consider that the microcontroller has to manage the weights of all synapses in the array. Together with the microcontroller system clock and the complexity of the update rule, an upper bound on the update frequency arises, which is approximately 1 second of biological time in the case of STDP, by 20.04.2017. However this bound is not well determined yet and with some tweaking one might get faster update rules.
The variability of the uncalibrated neuron of the DLS prototype is similar to the calibrated in the BrainScaleS system. This is mostly due to the newly designed analog parameter storage, which also can be reconfigured faster and more reliably than the one in HICANN. The microcontroller that administrates the synaptic updates is also referred to as the plasticity processing unit, PPU.
Spikey is the oldest platform of the above mentioned ones and is documented here.
| Feature | Spikey | BrainscaleS | HICANN-DLS |
|---|---|---|---|
| neurons per chip | 384 | 512 | 32 |
| neuron type | conductance based AdEx | conductance based AdEx | current based LIF |
| system expandable to multiple chips | no | yes | no |
| Speedup | 104 | 104 | 103 |
| Synaptic weight resolution | 4-bit | 4-bit | 6-bit |
| STP | yes (either facilitating or depressing) | no | yes (must be implemented by yourself) |
| STDP | yes (fixed rule for weight update) | no | yes (must be implemented by yourself) |
| PyNN interface | yes | yes | no |
| Software abstraction | high | high | low |
- Brüderle, Daniel, et al. "A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems." Biological cybernetics 104.4-5 (2011): 263-296.
- Petrovici, Mihai A., et al. "Characterization and compensation of network-level anomalies in mixed-signal neuromorphic modeling platforms." PloS one 9.10 (2014): e108590.
- Thesis from Klähn/Heidelberg -- Up-to-date information about the hardware