fix(sim): fix timer core simulation

IObundle · Oct 12, 2023 · 613c78c · 613c78c
1 parent 44a6ee0
commit 613c78c
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Showing 2 changed files with 13 additions and 7 deletions.
diff --git a/hardware/simulation/src/timer_tb.v b/hardware/simulation/src/timer_tb.v
@@ -9,12 +9,14 @@ module timer_tb;
 
    integer fd;
 
+   reg clk;
    `IOB_CLOCK(clk, PER)
+
    reg rst;
 
-   `IOB_VAR(TIMER_ENABLE, 1)
-   `IOB_VAR(TIMER_SAMPLE, 1)
-   `IOB_WIRE(TIMER_VALUE, 2 * DATA_W)
+   reg TIMER_ENABLE;
+   reg TIMER_SAMPLE;
+   wire [2*DATA_W-1:0] TIMER_VALUE;
 
    initial begin
 `ifdef VCD
@@ -57,12 +59,13 @@ module timer_tb;
 
    //instantiate timer core
    timer_core timer0 (
-      .TIMER_ENABLE(TIMER_ENABLE),
-      .TIMER_SAMPLE(TIMER_SAMPLE),
-      .TIMER_VALUE (TIMER_VALUE),
+      .en_i(TIMER_ENABLE),
+      .rstrb_i(TIMER_SAMPLE),
+      .time_o(TIMER_VALUE),
       .clk_i       (clk),
       .cke_i       (1'b1),
-      .arst_i      (rst)
+      .arst_i      (rst),
+      .rst_i       (rst)
    );
 
 endmodule
diff --git a/iob_timer.py b/iob_timer.py
@@ -8,6 +8,7 @@
 # Submodules
 from iob_utils import iob_utils
 from iob_reg_re import iob_reg_re
+from iob_reg_e import iob_reg_e
 from iob_counter import iob_counter
 
 
@@ -25,10 +26,12 @@ def _create_submodules_list(cls):
                 # Hardware headers & modules
                 {"interface": "iob_s_port"},
                 {"interface": "iob_s_portmap"},
+                {"interface": "iob_wire"},
                 {"interface": "clk_en_rst_s_s_portmap"},
                 {"interface": "clk_en_rst_s_port"},
                 iob_utils,
                 iob_reg_re,
+                iob_reg_e,
                 iob_counter,
             ]
         )