Merge pull request riscv#862 from pdonahue-ventana/chapter-names

Update chapter names per ARC review feedback
JanMatCodasip · Aug 15, 2023 · 3c75bf3 · 3c75bf3
2 parents f95a676 + 2c19654
commit 3c75bf3
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diff --git a/Sdext.tex b/Sdext.tex
@@ -1,4 +1,4 @@
-\chapter{Sdext ISA Extension}
+\chapter{Sdext (ISA Extension)}
 \label{sec:core_debug}
 
 This chapter describes the Sdext ISA extension. It must be implemented to make

diff --git a/Sdtrig.tex b/Sdtrig.tex
@@ -1,4 +1,4 @@
-\chapter{Sdtrig ISA Extension}
+\chapter{Sdtrig (ISA Extension)}
 \label{sec:trigger}
 
 This chapter describes the Sdtrig ISA extension, which can be implemented

diff --git a/debug_module.tex b/debug_module.tex
@@ -1,4 +1,4 @@
-\chapter{Debug Module (DM), non-ISA} \label{chap:dm}
+\chapter{Debug Module (DM) (non-ISA extension)} \label{chap:dm}
 
 \begin{steps}{The Debug Module implements a translation interface between abstract debug
     operations and their specific implementation. It might support the following

diff --git a/dtm.tex b/dtm.tex
@@ -1,4 +1,4 @@
-\chapter{Debug Transport Module (DTM), non-ISA} \label{dtm}
+\chapter{Debug Transport Module (DTM) (non-ISA extension)} \label{dtm}
 
 Debug Transport Modules provide access to the DM over one or more transports
 (e.g.\ JTAG or USB).