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impl.tcl
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impl.tcl
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#Generated by Fabric Compiler ( version 2020.3-Lite <build 71107> ) at Tue Oct 25 17:32:39 2022
report_power
gen_netlist
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
pnr
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
pnr
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
add_design D:/panguprj/tinydram/ipcore/pll/pll.idf
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
synthesize -ads -selected_syn_tool_opt 2
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
dev_map
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
add_design "D:/panguprj/tinydram/source/top.v"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module top
synthesize -ads -selected_syn_tool_opt 2
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
report_power
gen_netlist
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream
remove_design -verilog "D:/panguprj/tinydram/source/top.v"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile -top_module tinyriscv_soc_top
synthesize -ads -selected_syn_tool_opt 2
dev_map
pnr
report_timing
gen_bit_stream