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tinydram.fdc
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tinydram.fdc
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define_attribute {p:halted_ind} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:halted_ind} {PAP_IO_LOC} {U10}
define_attribute {p:halted_ind} {PAP_IO_VCCIO} {3.3}
define_attribute {p:halted_ind} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:halted_ind} {PAP_IO_DRIVE} {4}
define_attribute {p:halted_ind} {PAP_IO_SLEW} {SLOW}
define_attribute {p:uart_tx_pin} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:uart_tx_pin} {PAP_IO_LOC} {R18}
define_attribute {p:uart_tx_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:uart_tx_pin} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:uart_tx_pin} {PAP_IO_DRIVE} {4}
define_attribute {p:uart_tx_pin} {PAP_IO_SLEW} {SLOW}
define_attribute {p:clk} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:clk} {PAP_IO_LOC} {B5}
define_attribute {p:clk} {PAP_IO_VCCIO} {3.3}
define_attribute {p:clk} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:rst_ext_i} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:rst_ext_i} {PAP_IO_LOC} {U12}
define_attribute {p:rst_ext_i} {PAP_IO_VCCIO} {3.3}
define_attribute {p:rst_ext_i} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:uart_rx_pin} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:uart_rx_pin} {PAP_IO_LOC} {N14}
define_attribute {p:uart_rx_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:uart_rx_pin} {PAP_IO_STANDARD} {LVTTL33}
create_clock -name {sys_clk} [get_ports {clk}] -period {20.000} -waveform {0.000 10.000} -add
define_attribute {n:jtag_TCK} {PAP_CLOCK_DEDICATED_ROUTE} {FALSE}
define_attribute {p:jtag_TDO} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:jtag_TDO} {PAP_IO_LOC} {V16}
define_attribute {p:jtag_TDO} {PAP_IO_VCCIO} {3.3}
define_attribute {p:jtag_TDO} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:jtag_TDO} {PAP_IO_DRIVE} {4}
define_attribute {p:jtag_TDO} {PAP_IO_SLEW} {SLOW}
define_attribute {p:jtag_TCK} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:jtag_TCK} {PAP_IO_LOC} {V17}
define_attribute {p:jtag_TCK} {PAP_IO_VCCIO} {3.3}
define_attribute {p:jtag_TCK} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:jtag_TDI} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:jtag_TDI} {PAP_IO_LOC} {V18}
define_attribute {p:jtag_TDI} {PAP_IO_VCCIO} {3.3}
define_attribute {p:jtag_TDI} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:jtag_TMS} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:jtag_TMS} {PAP_IO_LOC} {T18}
define_attribute {p:jtag_TMS} {PAP_IO_VCCIO} {3.3}
define_attribute {p:jtag_TMS} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:gpio[1]} {PAP_IO_DIRECTION} {INOUT}
define_attribute {p:gpio[1]} {PAP_IO_LOC} {P17}
define_attribute {p:gpio[1]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:gpio[1]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:gpio[1]} {PAP_IO_DRIVE} {4}
define_attribute {p:gpio[1]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:gpio[0]} {PAP_IO_DIRECTION} {INOUT}
define_attribute {p:gpio[0]} {PAP_IO_LOC} {U11}
define_attribute {p:gpio[0]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:gpio[0]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:gpio[0]} {PAP_IO_DRIVE} {4}
define_attribute {p:gpio[0]} {PAP_IO_SLEW} {SLOW}