LoopVectorization without AVX512?

[SkyWorld117]

It seems Intel has decided to keep AVX512 only as an instruction for sever chips (like the Xeon series). It has started to disable AVX512 on the 12th gen consumer chips by overwriting the microcodes. It probably means a significant increasment of execution time for LV.

However, I have noticed that Intel keeps VNNI for all lines to support machine learning. As far as I understood, it is an instruction based on AVX512. Could that be a possible way out?

[chriselrod]

This is true for Alder Lake at least, and probably will be true for all CPUs paired with gracemont small cores.

Perhaps a future generation of small cores will add AVX512 support, which will allow them to enable it on the big cores again.
Or maybe there'll be a software solution.
Adding minimal AVX512 support should be fairly cheap.
E.g., Zen1 supported AVX(2)'s 256 bit operations by basically decomposing them into two 128-bit uops.
This meant it didn't really get much speed up from 256 bit vs 128 bit, but, they worked.

Rumor has it that Zen4 will support AVX512.

As for AVX512 VNNI and the AVX VNNI that Alder Lake does support -- LoopVectorization currently does not support either of them.
I'll probably add support for these in the LoopVectorization rewrite eventually.
Perhaps sooner, if it turns out I need it for work.

Of course, others are welcome to add support for these with PRs.