This RISC-V core includes custom modules and custom instructions for the transformer's attention operations. The core was implemented on the zynq7000 board in verilogHDL. Other details will be added at a later date.
[1] The RV32I core based on https://github.com/georgeyhere/Toast-RV32i [2] The custom instruction set was based on this paper. Q. Jiao, W. Hu, F. Liu and Y. Dong, "RISC-VTF: RISC-V Based Extended Instruction Set for Transformer," 2021 IEEE International Conference on Systems, Man, and Cybernetics (SMC), Melbourne, Australia, 2021, pp. 1565-1570.