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34 Open 14 Closed
34 Open 14 Closed
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Issues list

riffa.py ctype type error due to float type entered into fpga_send length argument
#65 opened Jun 24, 2024 by dsdy120
fpga_send loop error
#63 opened Apr 7, 2024 by xlyzzz
8+ fpgas
#59 opened Apr 22, 2023 by werwolf
A question about testutil.c
#57 opened Mar 7, 2022 by emesjx
Executed ./testutil 0 command displaying 0 devices, but use lspci displaying Xilinx Corporation Device 7028, anybody know why?
#56 opened Jul 4, 2021 by qingcai52
1
Build succes on Win10 but the resulting driver fails
#54 opened May 20, 2021 by pmaBSA
a big riffa bugs
#50 opened Dec 11, 2019 by hushunkui
PCIe Gen2.0x16 or PCIe Gen3.0x16 support
#49 opened Dec 5, 2019 by jixi2018
1
RIFFA Virtex 6 series BAR memory area read write
#48 opened Oct 16, 2019 by briansune
Riffa simulation
#47 opened Sep 6, 2019 by jixi2018
fpga_recv timeout
#46 opened Aug 29, 2019 by bix010
file include issue on functions.vh
#45 opened Aug 15, 2019 by gxflying
riffa python example showed different data between TX and RX buffers
#44 opened Aug 14, 2019 by jixi2018
3
I want riffa 2.1 for spartan6
#42 opened Jul 22, 2019 by tanbakoo
PCIe x1 gen 2
#41 opened May 24, 2019 by CedricDly
ERROR: [VRFC 10-1775] range must be bounded by constant expressions
#40 opened Feb 14, 2019 by YiSyuanChen
3
calculation of config_link_rate is off for VC709
#39 opened Feb 5, 2019 by hmaarrfk
wSchedule throws warnings for not being set in Vivado 2018.3
#38 opened Feb 4, 2019 by hmaarrfk
6
Why are the first four received words not as expected?
#35 opened Jan 2, 2019 by Johnhave
1
Bulk data from PC to FPGA with slow user logic
#34 opened Dec 7, 2018 by quangdaovu
1
riffa——learn
#33 opened Nov 29, 2018 by moptutu
unable to resolve clog2s?
#32 opened Nov 21, 2018 by Jzone315
2
chnl_tester state machine flow issue
#30 opened Mar 10, 2018 by buttercutter
8
Bandwidth drops for linux
#29 opened Feb 28, 2018 by buttercutter
13
verilator testbench support
#28 opened Feb 2, 2018 by buttercutter
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