wSchedule throws warnings for not being set in Vivado 2018.3

[hmaarrfk]

riffa/fpga/riffa_hdl/tx_alignment_pipeline.v

Line 163 in 4e9d3c8

wire [C_CLOG_MUX_INPUTS-1:0] wSchedule[C_NUM_MUXES-1:0][(1<<(3+C_CLOG_MAX_SCHEDULE))-1:0];

Going through the verilog code, it appears to never be set. Did something get dropped in a recent version?

[hmaarrfk]

I guess they are set in schedules.vh which is included.

In schedules.vh there is a comment stating that it is a sin to do what they did.....

[drichmond]

Guilty

…

On Feb 4, 2019, at 9:35 AM, Mark Harfouche ***@***.***> wrote: I guess they are set in schedules.vh which is included. In schedules.vh there is a comment stating that it is a sin to do what they did..... — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#38 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AGFUdC06rNCQKQZsQ7ousfkdnuLh1lF5ks5vKG9MgaJpZM4ahrIk>.

[hmaarrfk]

I copied the whole generate statement in the tx_alignment_pipeline but the warning persists

[Synth 8-3848] Net wSchedule[0][31] in module/entity tx_alignment_pipeline does not have driver. ["/home/mark2/git/riffa/fpga/riffa_hdl/tx_alignment_pipeline.v":163]

The design is for PCIE with
C_DATA_WIDTH = 128

[hmaarrfk]

Do you think these warnings are benign? They seem quite serious, though there are some other ones that scare me more for now.

I'm trying to port to Ultrascale+, so these warnings are helping me tie down loose ends.

[drichmond]

Are you porting to 256 bits?

I suspect these warnings are fine. The issue is that I didn't define the complete ROM for wSchedule, and Vivado is informing you of this.

[hmaarrfk]

Not yet. I have a ZCU106, it only has a PCIE 3.0 x4 connector. So i set the core to 128 bits.

Some things changed annoyingly (one hot vs number as outputs for configurations for the PCIe core).

I'm down to 0 critical warnings, and about 4-7 lines of regular "warnings" for riffa.