Add trigger output

api/scaffold/__init__.py

@@ -1625,21 +1625,24 @@ def __init__(self, parent):
         """
         super().__init__(parent, "/swd")
         # Declare the signals
-        self.add_signals("swclk", "swd_in", "swd_out")
+        self.add_signals("swclk", "swd_in", "swd_out", "trigger")
         # Declare the registers
         self.__addr_base = base = 0x0b00
         self.add_register("rdata", "rv", base)
         self.add_register("wdata", "w", base + 4, reset=0x00)
         self.add_register("status", "rv", base + 0x10)
         self.add_register("cmd", "w", base + 0x20)
 
-    def reset(self):
+    def reset(self, trigger=False):
         """
         Reset the debug interface. This emits a reset sequence, followed by
         the JTAG-to-SWD select sequence and a second reset sequence. The deviceid
         register is then read.
         """
-        self.reg_cmd.write(0x80)
+        val = 0x80
+        if trigger:
+            val = val | (1 << 6)
+        self.reg_cmd.write(val)
         self.read(0, 0)
         return self.status()
 
@@ -2340,6 +2343,8 @@ def connect(
                 self.add_mtxl_in(f"/pgen{i}/out")
             for i in range(len(self.chains)):
                 self.add_mtxl_in(f"/chain{i}/trigger")
+        if self.version >= parse_version("0.10"):
+            self.add_mtxl_in(f"/swd/trigger")
 
         # FPGA left matrix output signals
         # Update this section when adding new modules with inputs
@@ -2397,6 +2402,7 @@ def connect(
         if self.version >= parse_version("0.10"):
             self.add_mtxr_in("/swd/swclk")
             self.add_mtxr_in("/swd/swd_out")
+            self.add_mtxr_in("/swd/trigger")
 
         # FPGA right matrix output signals
         self.add_mtxr_out("/io/a0")

fpga-arch/bsv/SWD.bsv

@@ -45,11 +45,13 @@ endinterface
 interface ScaffoldSWDModule;
     (* prefix="" *) interface ScaffoldBus bus;
     (* prefix="" *) interface SWDControllerPins pins;
+    (* always_ready, prefix="" *) method Bit#(1) trigger;
 endinterface
 
 typedef struct {
     Bit#(1) reset;
-    Bit#(3) reserved;
+    Bit#(1) trigger;
+    Bit#(2) reserved;
     Bit#(1) apndp;
     Bit#(1) rnw;
     Bit#(2) addr;
@@ -77,6 +79,8 @@ module swd_module (ScaffoldSWDModule);
     Reg#(Bit#(8)) bus_reg_rdata <- mkRegA(0);
     Reg#(Bit#(8)) bus_reg_status <- mkRegA(0);
 
+    PulseWire trig <- mkPulseWire();
+
     Reg#(Vector#(4, Bit#(8))) rdata <- mkRegA(unpack(0));
     Reg#(Status) status <- mkRegA(unpack(0));
     Reg#(Vector#(4, Bit#(8))) wdata <- mkRegA(unpack(0));
@@ -131,6 +135,10 @@ module swd_module (ScaffoldSWDModule);
             );
             state <= RW;
         end
+
+        if (new_cmd.trigger == 1) begin
+            trig.send();
+        end
     endrule
 
     rule do_reset (state == RESET);
@@ -184,4 +192,6 @@ module swd_module (ScaffoldSWDModule);
     endinterface
 
     interface SWDControllerPins pins = swd_controller.pins;
+
+    method Bit#(1) trigger = pack(trig);
 endmodule

fpga-arch/bsv/SWDInner.bsv

@@ -157,7 +157,7 @@ module mkSWDController (SWDController#(clk_divider))
     PulseWire reset_in <- mkPulseWire();
 
     rule do_prescaler;
-        if (request_in) begin
+        if (request_in || reset_in) begin
             prescaler.reset();
         end
     endrule