Overview

This is a single board computer based on Motorola 68000. It features:

• 512kiB to 8MiB DRAM (SIMM 30 pins x2)
• basic memory protection / paging
• 8bits expansion bus with 4 slots
• PS/2 keyboard and mouse support
• serial link (TTL)
• boot with serial bootstrap or user flash

Some pictures here.

The block diagram below depicts the board architecture:

Board glue logic

Most board glue logic is implemented with an Altera EPM7128S CPLD. This part is obsolete but modern replacement exists with Actel Microsemi Microchip ATF1508AS (never tested though). The CPLD implements:

• DRAM address multiplexing
• DRAM refresh
• basic memory management: base address translation and inbound check with power of two alignment constraints
• 8-bits expansion bus access, for 8-bits wide or 16-bits wide memory cycle from the 68000
• first stage boot procedure, by copying during reset the 512 first bytes from the flash memory (see MFP chip description below) at address 000000h in DRAM.

Expansion bus also uses a few discrete logic (74245 buffers and 74138 address decoder).

An additional 74148 encodes interrupt sources to CPU IPL0/1/2.

memory management

The CPLD provides very basic memory management capabilities, for user mode accesses only (FC2 set to 0). It relies on two value set with four registers. These registers are write only, 16-bits, but only the upper bit 15:8 are used.

register	address	description
MMU_BASE_LO	FE0000h	base address bits 19:12
MMU_BASE_HI	FE0002h	base address bits 22:20
MMU_MASK_LO	FE0004h	address mask bits 19:12
MMU_MASK_HI	FE0006h	address mask bits 21:20

Any user address is and'ed with MMU_MASK then or'ed with MMU_BASE. It results in a memory area allocated to a user program with a power of two size, with a base address aligned to its own size. Any user access that targets an address above the allocated size ends with a bus error.

interrupt management

The autovectored interrupt scheme is used (VPA# assertion). To save pins on the CPLD the FC0 and FC1 are not available to identify an interrupt acknowledge cycle, so any read cycle at FFFFFFh with FC2 set to 1 is considered as such.

8-bits expansion bus

This bus provides access to 5 peripherals:

• 4 available through dedicated connectors (2x10 female pin headers)
• 1 embeded to the board: the MFP

It provides for each peripheral up to 128kiB aperture into CPU memory space.

The table below lists the signals on this bus as seen for each slot.

signal	type	shared	description
RST#	input	yes	system reset
CE#	input	no	access enable
ACK#	open drain output	yes	access acknowledge
WE#	input	yes	write enable
ALE#	input	yes	address latch enable
IRQ#	open drain output	option	interrupt request
A0	input	yes	address bit 0
AD[7:0]	bidir	yes	address / data

single access cycles

This is how translates a byte access from the 68000 (UDS# or LDS# alone)

note: peripherals like the MFP ignore the address bits 16:1 and can ignore the ALE# signal.

multiple access cycles

This is how translates a 16-bits access from the 68000 (UDS# and LDS#)

Bootstrap loading

Right after a reset, the CPLD starts by transfering 512 bytes of data from the MFP FLASH_DATA register into the first bytes of DRAM. Then the very first 68000 memory access (at 0000000h) is performed.

Because any software is to be much bigger than just 512-bytes, this chunk of code must itself include assembly instructions to copy the rest of the code - still accessing FLASH_DATA register.

The MFP contains two software images for the 68000:

• a serial bootstrap, loading from the serial interface the binary to jump in, that is enables by pressing 's' key on a keyboard plugged into the PS/2 port
• or an embedded binary to jump in.

To change the embedded binary, the MFP firmware must be recompiled and programmed (the 68000 binary is a constant data table within the microcontroller firmware).

MFP (multifunction peripheral)

This is a software defined chip base on a PIC18F27K42 microcontroller. It provides:

• embedded flash with 2 software images for the 68000, selection by detecting pressed key at reset.
• IOs/timer with dedicated low-priority interrupt: two PS/2 port, one serial link, 1 kHz RTC timer
• 250 Hz system timer with dedicated highest-priority interrupt
• hard/soft reset
• debug register (POST or so)

The MFP has only two memory locations accessible through the expansion bus: one to set the actual register to access, the other to read or write data from/to the register.

register	address	description
MFP_DATA	F00000h	MFP register data
MFP_ADDRESS	F00001h	MFP register index

Register set

register	index	description
FLASH_DATA	0	boot flash data access. flash data pointer auto increments
TICKS	3	4-us ticks counter, 0-249
UART_STS	4	UART status bit 7: TX ready bit 1: RX FIFO overflow bit 0: RX FIFO underflow
UART_DATA	5	UART data in/out
POST	7	POST code (debug)
PS2P0_STS	8	PS/2 port 0 status bit 0: data available
PS2P0_DATA	9	PS/2 port 0 data
PS2P1_STS	10	PS/2 port 1 status bit 0: data available
PS2P1_DATA	11	PS/2 port 1 data
SYSCFG	12	system tick configuration bit 0: enable timer interrupt bit 5: set by bootstap loader to prevent flash to RAM boot transfer bit 6: enable self immediate interrupt bit 7: soft reset
SYSSTS	13	system tick status bit 0: timer interrupt pending bit 6: self immediate interrupt pending
IRQCFG	14	interrupt controller configuration bit 0: enable RTC interrupt bit 1: enable PS/2 keyboard interrupt bit 2: enable PS/2 mouse interrupt bit 3: enable UART RX interrupt
IRQSTS	15	interrupt controller status bit 0: RTC interrupt pending bit 1: PS/2 keyboard interrupt pending bit 2: PS/2 mouse interrupt pending bit 3: UART RX interrupt pending

Memory mapping

memory range	access	size	memory area
000000h - 7FFFFFh	U/S	8MiB	DRAM. memory address translation/mask/check for user mode only
800000h - EFFFFFh	S	7MiB	DO NOT USE. mirrors F00000h - FFFFFFh
F00000h - F1FFFFh	S	128kiB	MFP registers. address bits 16:1 are ignored
F20000h - F3FFFFh	S	128kiB	expansion bus connector J9
F40000h - F5FFFFh	S	128kiB	expansion bus connector J11
F60000h - F7FFFFh	S	128kiB	DO NOT USE. reserved for expansion bus hardware implementation
F80000h - F9FFFFh	U*/S	128kiB	expansion bus connector J10. *: user access to be removed
FA0000h - FBFFFFh	S	128kiB	DO NOT USE. unmapped, might be used for another peripheral slot
FC0000h - FDFFFFh	S	128kiB	expansion bus connector J8
FE0000h - FFFFFFh	S	128kiB	restricted to PMMU register configuration

BOM

This table below is no spec, it just shows the parts that equip the board on my desk.

Reference	Part
RN1	not populated
U1	MC68HC000FN20
U2	74F138
U3, U6, U7	74F245
U4	EPM7128SLC84-10
U5	PIC18F27K42SP
U8	74HC148
X2	12-MHz