fuse.log

Running: X:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o X:/Xilinx/Memari/Exp06/reg_gate_tb_isim_beh.exe -prj X:/Xilinx/Memari/Exp06/reg_gate_tb_beh.prj work.reg_gate_tb 
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Parsing VHDL file "X:/Xilinx/Memari/Exp06/dff.vhd" into library work
Parsing VHDL file "X:/Xilinx/Memari/Exp06/decoder2to4.vhd" into library work
Parsing VHDL file "X:/Xilinx/Memari/Exp06/register_gate.vhd" into library work
Parsing VHDL file "X:/Xilinx/Memari/Exp06/reg_gate_tb.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling architecture behavioral of entity decoder2to4 [decoder2to4_default]
Compiling architecture behavioral of entity dff [dff_default]
Compiling architecture behavioral of entity register_gate [register_gate_default]
Compiling architecture test of entity reg_gate_tb
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 9 VHDL Units
Built simulation executable X:/Xilinx/Memari/Exp06/reg_gate_tb_isim_beh.exe
Fuse Memory Usage: 29360 KB
Fuse CPU Usage: 1421 ms