Merged CoreTSE example code version 2.5.117.

Mi-V-Soft-RISC-V · Dec 18, 2023 · 7495601 · 7495601
2 parents 1a30e5d + f6611c3
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diff --git a/driver-examples/CoreTSE/miv-rv32-coretse-packet_tx_rx/README.md b/driver-examples/CoreTSE/miv-rv32-coretse-packet_tx_rx/README.md
@@ -3,9 +3,9 @@
 This example project demonstrates the use of CoreTSE driver APIs implementing a
 transmit and receive packet application.
 
-There are 2 different build configurations provided with this project which
+There are two different build configurations provided with this project which
 configure this SoftConsole project for RISC-V IMC instruction extension.
-The Following configurations are provided with the example.
+The following configurations are provided with the example.
 
 - miv-rv32-imc-debug
 - miv-rv32-imc-release
@@ -47,14 +47,18 @@ to STDIO, etc.
 
 ## Target hardware
 
-This project has been tested on the following boards with the MIV_RV32 IMC Core:
+This project has been tested on the following board with the MIV_RV32 IMC Core:
 
 - PolarFire Evaluation Kit (MPF300-EVAL-KIT)
-- Arrow Electronics Everest Board (MPF300T)
 
-Both the PolarFire Evaluation Kit and the Everest Board use Microchip's VSC8575 PHY.
+The PolarFire Evaluation Kit uses Microchip's VSC8575 PHY.
 The driver for this PHY can be found in the CoreTSE driver directory, `src/platform/drivers/fpga_ip/CoreTSE`.
 
+This project uses a custom hardware design that can be found in the
+[Application Note: AN4569][1].
+
+[1]: https://www.microchip.com/en-us/application-notes/an4569
+
 ## Modifying this example to target other boards or interfaces
 
 Refer to the `src/application/config.h` to configure a the project to target a different

diff --git a/...oretse-packet_tx_rx/src/boards/polarfire-eval-kit/fpga_design_config/fpga_design_config.h b/...oretse-packet_tx_rx/src/boards/polarfire-eval-kit/fpga_design_config/fpga_design_config.h
@@ -43,16 +43,15 @@
  * <corename>_<instance>_BASE_ADDR
  */
 #define COREUARTAPB0_BASE_ADDR          0x60000000UL
+#define CORESPI_BASE_ADDR               0x60001000UL
+#define COREGPIO_OUT_BASE_ADDR          0x60003000UL
+#define PF_CORE_SYSTEM_SERVICES         0x60004000UL
 
 #define TSE_BASEADDR                    0x70000000UL
 #define TSE_DESC                        0x71000000UL
 #define TSE_TX_BUF                      0x72000000UL
 #define TSE_RX_BUF                      0x72001000UL
 
-#define CORESPI_BASE_ADDR               0x60001000UL
-#define COREGPIO_OUT_BASE_ADDR          0x60003000UL
-
-
 
 /***************************************************************************//**
  * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor